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| gs4911b/gs4910b hd/sd/grap hics clock and timing generator with genlock 1 of 119 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 www.gennum.com key features video clock synthesis ? generates any video or graphics clock up to 165mhz ? pre-programmed for 8 video and 13 graphics clocks ? accuracy of free-running clock frequency limited only by crystal reference ? one differential and two sing le-ended video/graphics clock outputs ? each clock may be individually delayed for skew control ? video output clock may be di rectly connected to gennum?s serializers for a smpte-compliant hd-sdi output audio clock synthesis (gs4911b only) ? three audio clock outputs ? generates any audio clock up to 512*96khz ? pre-programmed for 7 audio clocks timing generation ? generates up to 8 timing signals at a time ? choose from 9 pre-programmed timing signals: h and v sync and blanking, f sync, f digital, afs (gs4911b only), display enable, 10fid, and up to 4 user-defined timing signals ? pre-programmed to generate ti ming for 35 different video formats and 13 different graphic display formats genlock capability ? clocks may be free-running or genlocked to an input reference with a variable offs et step size of 100-200ps (depending on exact clock frequency) ? variable timing offset step size of 100-200ps up to one frame ? output may be cross-locked to a different input reference ? freeze operation on loss of reference ? optional crash or drift lock on application of reference ? automatic input format detection general features ? reduces design complexity and saves board space - 9mm x 9mm package plus crystal reference replaces multiple vcxos, plls and timing generators ? pb-free and rohs compliant ? low power operation typically 300mw ? 1.8v core and 1.8v or 3.3v i/o power supplies ? 64-pin qfn package applications ? video cameras; digital audio and/or video recording/play back devices; digital audio and/ or video processing devices; computer/video displays; dvd/mpeg devices; digital set top boxes; video projectors; high definition video systems; multi-media pc applications description the gs4911b is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. it can be used to generate video and audio clocks and timing signals, and allows multiple devices to be genlocked to an input reference. the gs4910b includes all the features of the gs4911b, but does not offer audio clocks or afs pulse generation. the gs4911b/gs4910b will recognize input reference signals conforming to 36 different video standards and 16 different graphic formats, and will genlock the output timing information to the incoming reference. the gs4911b/gs4910b supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. the user may select to output on e of 8 different video sample clock rates or 13 different grap hic display clock rates, or may program any clock frequency between 13.5mhz and 165mhz. the chosen clock frequency can be further divided using internal dividers, and is available on two video clock outputs and one lvds video clock output pair. the video clocks are frequency and phased-locked to the horizontal timing reference, and can be individually delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the foll owing timing signals for 35 different video formats and 13 diff erent graphics formats: hsync, hblanking, vsync, vb lanking, f sync, f di gital, afs (gs4911b only), de, and 10fid. these timing outputs may be locked to the input reference signal for genlock timing and may be phase adjusted via internal registers. in addition, the gs4911b provi des three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7khz to 96khz. audio to vi deo phasing is accomplished by an external 10fid input reference, a 10fid signal specified via internal registers, or a user- programmed audio frame sequence. the gs4911b/gs4910b is pb-free, and the encapsulation compound does not contain hal ogenated flame retardant (rohs compliant).
gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 2 of 119 gs4911b functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide audio clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid lock_lost ref_lost vid_std[5:0] asr_sel[2:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 aclk1 aclk2 aclk3 pclk3 genlock pclk aclk_512 aclk_384 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync afs gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 3 of 119 gs4910b functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid ref_lost vid_std[5:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 pclk3 genlock pclk 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync lock_lost gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 4 of 119 revision history version ecr pcn date changes and/or modifications 5 151938 ? j une 2009 up d ate d d o c ument with new template. 4 144904 ? april 2007 c orre c te d h_offset value in 3.2.1.1 g enlo c k timin g offset . 3 141424 40495 au g ust 200 6 up d ate d terminal wi d th to 0.25+/-0.05 on pa c ka g e dimensions an d pin 1 id c han g e to 45 c hamfer. 2 139291 38723 april 200 6c orre c te d d es c ription an d formulas for loop b an d wi d th. c onverte d to data s heet. c larifie d settin g of vid_ s td in exten d e d au d io mo d e. up d ate d power c onsumption of gs 4910b. 1 1388 66 37792 de c em b er 2005 c orre c te d phrasin g re g ar d in g user-pro g ramma b le outputs. a dd e d note on v blankin g output wi d th for vid_ s td=4, 6 , 8. c orre c te d e s d prote c tion to 1kv. 0 138004 ? novem b er 2005 new d o c ument. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 5 of 119 contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 revision history ............................................................................................................... ..................................4 1. pin out..................................................................................................................... ..........................................8 1.1 gs4911b pin assignment .................................................................................................... ...........8 1.2 gs4910b pin assignment .................................................................................................... ...........9 1.3 pin descriptions .......................................................................................................... ................... 10 1.4 pre-programmed recognized vide o and graphics standards ....... ........ ......... ......... ..... 20 1.5 output timing signals ..................................................................................................... ............ 26 2. electrical characteristics .................................................................................................. ....................... 30 2.1 absolute maximum ratings .................................................................................................. ..... 30 2.2 dc electrical characteristics ...... ....................................................................................... ........ 30 2.3 ac electrical characterist ics ............................................................................................. ........ 33 3. detailed description........................................................................................................ .......................... 37 3.1 functional overview ....................................................................................................... ............. 37 3.2 modes of operation ........................................................................................................ .............. 37 3.2.1 genlock mode............................................................................................................. ........ 38 3.2.2 free run mode ............................................................................................................ ....... 41 3.3 output timing format selection ............................................................................................ .. 42 3.4 input reference signals ................................................................................................... ............ 43 3.4.1 hsync, vsync, and fsync.......................................................................................... 43 3.4.2 10fid .................................................................................................................... ................. 44 3.4.3 automatic polarity recognition .... ........... .......... ........... ........... ........... ........... ......... ..... 45 3.5 reference format detector ................................................................................................. ....... 45 3.5.1 horizontal and vertical timing characte ristic measurements ......................... 45 3.5.2 input reference validity................................................................................................. 46 3.5.3 behaviour on loss and re-acquisition of the reference signal......................... 47 3.5.4 allowable frequency drift on the reference .......................................................... 49 3.6 genlock ................................................................................................................... .......................... 50 3.6.1 automatic locking process ............................................................................................ 50 3.6.2 manual locking process.................................................................................................. 5 4 3.6.3 adjustable locking time................................................................................................. 5 8 3.6.4 adjustable loop bandwidth .......................................................................................... 58 3.6.5 locking to digital timing from a deserializer ......................................................... 60 3.7 clock synthesis ........................................................................................................... ................... 61 3.7.1 video clock synthesis.................................................................................................... .. 61 3.7.2 audio clock synthesis (gs4911b only)...................................................................... 63 3.8 video timing generator .................................................................................................... .......... 67 3.8.1 10 field id pulse........................................................................................................ ......... 67 3.8.2 audio frame synchronizing pulse (gs4911b only)............................................... 68 3.8.3 user_1~4 ................................................................................................................. ............ 69 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 6 of 119 3.8.4 timing_out pins .......................................................................................................... ... 71 3.9 custom clock generation ................................................................................................... ........ 72 3.9.1 programming a custom video clock.......................................................................... 72 3.9.2 programming a custom audio clock (gs4911b only) .......................................... 73 3.10 custom output timing signal generation ......................................................................... 74 3.10.1 custom input reference ............................................................................................... 75 3.11 extended audio mode for hd demux using the gennum audio core ................... 75 3.12 gspi host interface ...................................................................................................... ............... 76 3.12.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 77 3.12.2 data read and write timing ....................................................................................... 78 3.12.3 configuration and status registers........................................................................... 79 3.13 jtag ..................................................................................................................... .......................... 110 3.14 device power-up .......................................................................................................... ............ 111 3.14.1 power supply sequencing ......................................................................................... 111 3.15 device reset ............................................................................................................. ................... 111 4. application reference design ................................................................................................ ............. 112 4.1 gs4911b typical application circuit ................................................................................... 112 4.2 gs4910b typical application circuit ................................................................................... 113 5. references & relevant standards ............................................................................................. .......... 114 6. package & ordering information .............................................................................................. .......... 115 6.1 package dimensions ........................................................................................................ ........... 115 6.2 solder reflow profiles .................................................................................................... ............ 116 6.3 recommended pcb footprint .. ........... ........... ........... ........... ........... ........... ........... ........... ....... 117 6.4 packaging data ............................................................................................................ ................. 117 6.5 ordering information ...................................................................................................... ........... 118 list of figures gs4911b functional block diagram ............................ .................................................................. ........... 2 gs4910b functional block diagram ............................ .................................................................. ........... 3 figure 1-1: xtal1 and xtal2 reference circuits .............. ................................................................ 20 figure 2-1: pclk to timing_out signal output timing .. ............................................................... 36 figure 3-1: hd-sd calculation ................................ ................................................................. ................. 40 figure 3-2: output accuracy and modes of operation ..................................................................... 42 figure 3-3: example hsync, vsync, and fsync analog input timing from a sync separator ................................................................................................................ ................................ 43 figure 3-4: example h blanking, v blanking, and f digital input timing from an sdi deserializer .............................................................................................................. ................................ 44 figure 3-5: 10fid input timing ................................................................................................ ................. 45 figure 3-6: internal video genlock block .................... .................................................................. ....... 54 figure 3-7: internal audio genlock block .................... .................................................................. ....... 56 figure 3-8: default 10fid output timing ....................................................................................... ....... 67 figure 3-9: optional 10fid output timing .................. .................................................................... ..... 68 figure 3-10: afs output timing ................................................................................................ ............... 69 figure 3-11: user programmable output signal ................ ................................................................ 70 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 7 of 119 figure 3-12: custom timing parameters ......................................................................................... ....... 74 figure 3-13: audio clock block diagram for hd demux operation ........................................... 76 figure 3-14: gspi application interface connection .......... .............................................................. 77 figure 3-15: command word format .............................................................................................. ....... 77 figure 3-16: data word format ................................................................................................. ............... 78 figure 3-17: gspi read mode timing ............................................................................................ ......... 79 figure 3-18: gspi write mode timing ....................... .................................................................... ......... 79 figure 3-19: in-circuit jtag .................................................................................................. .................. 110 figure 3-20: system jtag ..................................... ................................................................. ................... 111 figure 6-1: maximum pb-free solder reflow profile (preferred) ................................................ 116 figure 6-2: standard pb solder reflow profile ................................................................................ .. 116 list of tables table 1-1: pin descriptions .................................................................................................... ..................... 10 table 1-2: recognized video and graphics standards ......... ............ ........... ........... ........... ........... .... 21 table 1-3: output timing signals ....... ........................................................................................ .............. 26 table 2-1: dc electrical characteristics ....................................................................................... .......... 30 table 2-2: ac electrical characteristics ....................................................................................... .......... 33 table 2-3: suggested external crystal specification .......... ............................................................... 36 table 3-1: clock_phase_offset[15:0] encoding scheme................................................................... 39 table 3-2: ambiguous standard identification................. .................................................................. . 47 table 3-3: max_ref_delta encoding scheme....................................................................................... 49 table 3-4: cross-reference genlock table....................................................................................... ...... 52 table 3-5: integer constant value.............................................................................................. .............. 57 table 3-6: video clock phase adjustment host settings.................................................................. 62 table 3-7: audio sample rate select............................................................................................ ........... 63 table 3-8: audio clock divider ................................ ................................................................. ................ 64 table 3-9: encoding scheme for afs_reset_window ...................................................................... 65 table 3-10: audio sampling frequency to video fr ame rate synchronization...................... 66 table 3-11: crosspoint select.................................................................................................. ................... 71 table 3-12: gspi timing parameters ............................................................................................. .......... 78 table 3-13: configuration and status registers................ ................................................................. .. 79 table 5-1: references & relevant standards ..................................................................................... . 114 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 8 of 119 1. pin out 1.1 gs4911b pin assignment lock_lost genlock 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd aud_pll_gnd aud_pll_vdd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd asr_sel0 asr_sel1 asr_sel2 io_vdd aclk3 aclk2 aclk1 vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host gs4911b 64-pin qfn (top view) gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 9 of 119 1.2 gs4910b pin assignment lock_lost genlock gs4910b 64-pin qfn (top view) 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd io_vdd nc nc nc vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host analog_gnd analog_gnd analog_gnd analog_gnd analog_gnd gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 10 of 119 1.3 pin descriptions table 1-1: pin descriptions pin number name timing ty p e description 1lo c k_lo s tnon s yn c hronous output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e hi g h if the output is not g enlo c ke d to the input. the gs 4911b/ gs 4910b monitors the output pixel/line c ounters, as well as the internal lo c k status from the g enlo c k b lo c k an d asserts lo c k_lo s t hi g h if it is d etermine d that the output is not g enlo c ke d to the input. this pin will b e low if the d evi c e su cc essfully g enlo c ks the output c lo c k an d timin g si g nals to the input referen c e. if lo c k_lo s t is low, the referen c e timin g g enerator outputs will b e phase lo c ke d to the d ete c te d referen c e si g nal, pro d u c in g an output in a cc or d an c e with the vi d eo stan d ar d sele c te d b y the vid_ s td[5:0] pins. 2ref_lo s tnon s yn c hronous output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e hi g h if: ? no input referen c e si g nal is applie d to the d evi c e; or ? the input referen c e applie d d oes not meet the minimum/maximum timin g requirements d es c ri b e d in s e c tion 3.5.2 on pa g e 4 6 . this pin will b e low otherwise. if the referen c e si g nal is remove d when the d evi c e is in g enlo c k mo d e, ref_lo s t will g o hi g h an d the gs 4911b/ gs 4910b will enter freeze mo d e (see s e c tion 3.2.1.2 on pa g e 41 ). 3 vid_pll_vdd ? power s upply most positive power supply c onne c tion for the vi d eo c lo c k synthesis internal b lo c k. c onne c t to +1.8v d c . 4 vid_pll_ g nd ? power s upply g roun d c onne c tion for the vi d eo c lo c k synthesis internal b lo c k. c onne c t to g nd. 5 xtal_vdd ? power s upply most positive power supply c onne c tion for the c rystal b uffer. c onne c t to either +1.8v d c or +3.3v d c . note: c onne c t to +3.3v for minimum output p c lk jitter. 6 x1 non s yn c hronous input analo g s i g nal input c onne c t to a 27mhz c rystal or a 27mhz external c lo c k sour c e. s ee fi g ure 1-1 . 7x2 non s yn c hronous output analo g s i g nal output c onne c t to a 27mhz c rystal, or leave this pin open c ir c uit if an external c lo c k sour c e is applie d to pin 6 . s ee fi g ure 1-1 . 8xtal_ g nd ? power s upply g roun d c onne c tion for the c rystal b uffer. c onne c t to g nd. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 11 of 119 9 c ore_ g nd ? power s upply g roun d c onne c tion for c ore an d i/o. s ol d er to the g roun d plane of the appli c ation b oar d . note: the c ore_ g nd pin shoul d b e sol d ere d to the same main g roun d plane as the expose d g roun d pa d on the b ottom of the d evi c e. 10 analo g _vdd ? power s upply most positive power supply c onne c tion for the analo g input b lo c k. c onne c t to +1.8v d c . 11, 20, 6 3n c ??do not c onne c t. 12 analo g _ g nd ? power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 13 aud_pll_ g nd ( gs 4911b only) ?power s upply g roun d c onne c tion for the au d io c lo c k synthesis internal b lo c k. c onne c t to g nd. analo g _ g nd ( gs 4910b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 14 aud_pll_vdd ( gs 4911b only) ?power s upply most positive power supply c onne c tion for the au d io c lo c k synthesis internal b lo c k. c onne c t to +1.8v d c . analo g _ g nd ( gs 4910b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 15 10fid non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the 10fid external referen c e si g nal is applie d to this pin b y the appli c ation layer. 10fid d efines the fiel d in whi c h the vi d eo an d au d io c lo c k phase relationship is d efine d a cc or d in g to s mpte 318-m. it is also use d to d efine a 3:2 vi d eo c a d en c e. note: if the input referen c e format d oes not in c lu d e a 10 fiel d id si g nal, this pin shoul d b e hel d low. s ee s e c tion 3.4.2 on pa g e 44 . 1 6 h s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the h s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. when the gs 4911b/ gs 4910b is operatin g in g enlo c k mo d e, the d evi c e senses the polarity of the h s yn c input automati c ally, an d referen c es to the lea d in g e dg e. if the user wishes to sele c t one of the pre-pro g ramme d vi d eo an d /or timin g output si g nals provi d e d b y the d evi c e, then this si g nal must a d here to one of the 3 6 d efine d vi d eo or 1 6 d ifferent g raphi c s d isplay stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the h s yn c input provi d es a horizontal s c annin g referen c e si g nal. the h s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 20 d es c ri b es the 3 6 vi d eo formats an d 1 6 g raphi c formats re c o g nize d b y the gs 4911b/ gs 4910b. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 12 of 119 17 v s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the v s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. when the gs 4911b/ gs 4910b is operatin g in g enlo c k mo d e, the d evi c e senses the polarity of the v s yn c input automati c ally, an d referen c es to the lea d in g e dg e. if the user wishes to sele c t one of the pre-pro g ramme d vi d eo an d /or timin g output si g nals provi d e d b y the d evi c e, then this si g nal must a d here to one of the 3 6 d efine d vi d eo or 1 6 d ifferent g raphi c s d isplay stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the v s yn c input provi d es a verti c al s c annin g referen c e si g nal. the v s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 20 d es c ri b es the 3 6 vi d eo formats an d 1 6 g raphi c formats re c o g nize d b y the gs 4911b/ gs 4910b. 18, 31, 38, 50, 6 2 io_vdd ? power s upply most positive power supply c onne c tion for the d i g ital i/o si g nals. c onne c t to either +1.8v d c or +3.3v d c . note: all five io_vdd pins must b e powere d b y the same volta g e. 19 f s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the f s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. the first fiel d is d efine d as the fiel d in whi c h the first b roa d pulse (also known as serration) is in the first half of a line. the f s yn c si g nal shoul d b e set hi g h d urin g the first fiel d for syn c - b ase d referen c es. if the user wishes to sele c t one of the pre-pro g ramme d vi d eo an d /or timin g output si g nals provi d e d b y the d evi c e, then this si g nal must a d here to one of the 3 6 d efine d vi d eo or 1 6 d ifferent g raphi c s d isplay stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the f s yn c input provi d es an o dd /even fiel d input referen c e. the f s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 20 d es c ri b es the 3 6 vi d eo formats an d 1 6 g raphi c formats re c o g nize d b y the gs 4911b/ gs 4910b. for b lankin g - b ase d referen c es, the f s yn c si g nal shoul d b e set hi g h d urin g the se c on d fiel d . note: if the input referen c e format d oes not in c lu d e an f syn c si g nal, this pin shoul d b e hel d low. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 13 of 119 27, 25, 24, 23, 22, 21 vid_ s td[5:0] non s yn c hronous input c ontrol s i g nal input s s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo s tan d ar d s ele c t. use d to sele c t the d esire d vi d eo/ g raphi c d isplay format for vi d eo c lo c k an d timin g si g nal g eneration. 8 d ifferent vi d eo an d 13 d ifferent g raphi c sample c lo c ks, as well as 35 d ifferent vi d eo format an d 13 d ifferent g raphi c format timin g si g nal outputs may b e sele c te d usin g these pins. for d etails on the supporte d vi d eo stan d ar d s an d vi d eo c lo c k frequen c y sele c tion, please see s e c tion 1.4 on pa g e 20 . 2 6 , 44 c ore_vdd ? power s upply most positive power supply c onne c tion for the d i g ital c ore. c onne c t to +1.8v d c . 28, 29, 30 a c lk1 a c lk2 a c lk3 ( gs 4911b only) ? output c lo c k s i g nal output s s i g nal levels are lv c mo s /lvttl c ompati b le. au d io output c lo c k si g nals. a c lk1, a c lk2, an d a c lk3 present au d io sample rate c lo c k outputs to the appli c ation layer. by d efault, after system reset, the au d io c lo c k output pins of the d evi c e provi d e c lo c k si g nals as follows: a c lk1 = 25 6 fs a c lk2 = 6 4fs a c lk3 = fs, where fs is the fun d amental samplin g frequen c y. the fun d amental samplin g frequen c y is sele c te d usin g a s r_ s el[2:0]. a dd itional samplin g frequen c ies may b e pro g ramme d in the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for ea c h of the au d io c lo c k outputs b y pro g rammin g d esi g nate d re g isters in the host interfa c e. c lo c k outputs of 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs an d z b it are sele c ta b le on a pin- b y-pin b asis. note: a c lk1-3 will have a 50% d uty c y c le, unless fs is sele c te d as 9 6 khz an d the host interfa c e is c onfi g ure d su c h that one of the three a c lk pins is set to output a c lo c k si g nal at 192fs or 384fs. if this is the c ase, then a 512fs c lo c k will have a 33% d uty c y c le. these si g nals will b e hi g h impe d an c e when a s r_ s el[2:0] = 000 b . n c ( gs 4910b only) ??do not c onne c t. 32, 33, 34 a s r_ s el[2:0] ( gs 4911b only) non s yn c hronous input c ontrol s i g nal input s s i g nal levels are lv c mo s /lvttl c ompati b le. au d io s ample rate s ele c t. use d to sele c t the fun d amental samplin g frequen c y, fs, of the au d io c lo c k outputs. s ee ta b le 3-7 . when a s r_ s el[2:0] = 000 b , au d io c lo c k g eneration will b e d isa b le d an d the a c lk1 to a c lk3 pins will b e hi g h impe d an c e. in this c ase, aud_pll_vdd (pin 14) may b e c onne c te d to g nd to minimize noise an d power c onsumption. analo g _ g nd ( gs 4910b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 14 of 119 35 timin g _out_1 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is h s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 3 6 timin g _out_2 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is h b lankin g . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 37 timin g _out_3 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is v s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 15 of 119 39 timin g _out_4 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is v b lankin g . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 40 timin g _out_5 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is f s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 41 timin g _out_ 6s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is f d i g ital. the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 16 of 119 42 timin g _out_7 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is 10 fiel d id (10fid). the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 43 timin g _out_8 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4911b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 2 6 for si g nal d es c riptions. note: default output is display ena b le (de). the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 45 lvd s /p c lk3_vdd ? power s upply most positive power supply c onne c tion for p c lk3 output c ir c uitry an d lvd s d river. c onne c t to +1.8v d c . 4 6 , 47 p c lk3 , p c lk3 ? output c lo c k s i g nal output s s i g nal levels are lvd s c ompati b le. differential vi d eo c lo c k output si g nal. p c lk3 / p c lk3 present a d ifferential vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, this output will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk3 / p c lk3 outputs b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . the p c lk3 / p c lk3 outputs will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 48 lvd s /p c lk3_ g nd ? power s upply g roun d c onne c tion for p c lk3 output c ir c uitry an d lvd s d river. c onne c t to g nd. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 17 of 119 49 p c lk2 ? output c lo c k s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo c lo c k output si g nal. p c lk2 presents a vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, the p c lk2 output pin will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk2 output b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . by settin g d esi g nate d re g isters in the host interfa c e, the c urrent d rive c apa b ility of this pin may b e set hi g h or low. by d efault, the c urrent d rive will b e low. it must b e set hi g h if the c lo c k rate is g reater than 100mhz. the p c lk2 output will b e hel d low when vid_ s td[5:0] = 00h. 51 p c lk1 ? output c lo c k s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo c lo c k output si g nal. p c lk1 presents a vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, the p c lk1 output pin will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk1 output b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . by settin g d esi g nate d re g isters in the host interfa c e, the c urrent d rive c apa b ility of this pin may b e set hi g h or low. by d efault, the c urrent d rive will b e low. it must b e set hi g h if the c lo c k rate is g reater than 100mhz. the p c lk1 output will b e hel d low when vid_ s td[5:0] = 00h. 52 p c lk1&2_ g nd ? power s upply g roun d c onne c tion for p c lk1&2 c ir c uitry. c onne c t to g nd. 53 p c lk1&2_vdd ? power s upply most positive power supply c onne c tion for p c lk1&2 c ir c uitry. c onne c t to +1.8v d c . 54 ph s _vdd ? power s upply most positive power supply c onne c tion for the vi d eo c lo c k phase shift internal b lo c k. c onne c t to +1.8v d c . 55 ph s _ g nd ? power s upply g roun d c onne c tion for the vi d eo c lo c k phase shift internal b lo c k. c onne c t to g nd. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 18 of 119 5 6j ta g /ho s t non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when set hi g h, cs _tm s , sc lk_t c lk, s dout_tdo, an d s din_tdi are c onfi g ure d for j ta g b oun d ary s c an testin g . when set low, cs _tm s , sc lk_t c lk, s dout_tdo, an d s din_tdi are c onfi g ure d as gs pi pins for normal host interfa c e operation. 57 sc lk_t c lk non s yn c hronous input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data c lo c k / test c lo c k. all j ta g / host interfa c e a dd ress an d d ata are shifte d into/out of the d evi c e syn c hronously with this c lo c k. host mo d e ( j ta g /ho s t = low): sc lk_t c lk operates as the host interfa c e serial d ata c lo c k, sc lk. j ta g test mo d e ( j ta g /ho s t = hi g h): sc lk_t c lk operates as the j ta g test c lo c k, t c lk. 58 s din_tdi s yn c hronous with sc lk_t c lk input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data input / test data input. host mo d e ( j ta g /ho s t = low): s din_tdi operates as the host interfa c e serial input, s din, use d to write a dd ress an d c onfi g uration information to the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h): s din_tdi operates as the j ta g test d ata input, tdi. 59 s dout_tdo s yn c hronous with sc lk_t c lk output s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data output / test data output. host mo d e ( j ta g /ho s t = low): s dout_tdo operates as the host interfa c e serial output, s dout, use d to rea d status an d c onfi g uration information from the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h): s dout_tdo operates as the j ta g test d ata output, tdo. 6 0 cs _tm ss yn c hronous with sc lk_t c lk input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. c hip s ele c t / test mo d e s ele c t. host mo d e ( j ta g /ho s t = low): cs _tm s operates as the host interfa c e c hip sele c t, cs , an d is a c tive low. j ta g test mo d e ( j ta g /ho s t = hi g h): cs _tm s operates as the j ta g test mo d e sele c t, tm s , an d is a c tive hi g h. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 19 of 119 6 1re s et non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to reset the internal operatin g c on d itions to their d efault settin g s or to reset the j ta g test sequen c e. host mo d e ( j ta g /ho s t = low): when asserte d low, all host re g isters an d fun c tional b lo c ks will b e set to their d efault c on d itions. all input an d output si g nals will b e c ome hi g h impe d an c e, ex c ept p c lk1 an d p c lk2, whi c h will b e set low. when set hi g h, normal operation of the d evi c e will resume. the user must hol d this pin low d urin g power-up an d for a minimum of 500 u s after the last supply has rea c he d its operatin g volta g e. j ta g test mo d e ( j ta g /ho s t = hi g h): when asserte d low, all host re g isters an d fun c tional b lo c ks will b e set to their d efault c on d itions an d the j ta g test sequen c e will b e hel d in reset. when set hi g h, normal operation of the j ta g test sequen c e will resume. 6 4 g enlo c k non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ts g enlo c k mo d e or free run mo d e. when this pin is set low an d the d evi c e has su cc essfully g enlo c ke d the output to the input referen c e, the d evi c e will enter g enlo c k mo d e. the vi d eo c lo c k an d timin g outputs will b e frequen c y an d phase lo c ke d to the d ete c te d referen c e si g nal. when this pin is set hi g h, the vi d eo c lo c k an d the referen c e-timin g g enerator will free-run. by d efault, the gs 4911b?s au d io c lo c ks will b e g enlo c ke d to the output vi d eo c lo c k re g ar d less of the settin g of this pin. note: the user must apply a referen c e to the input of the d evi c e prior to settin g g enlo c k = low. if the g enlo c k pin is set low an d no referen c e si g nal is present, the g enerate d c lo c k an d timin g outputs of the d evi c e may c orrespon d to the internal d efault settin g s of the c hip until a referen c e is applie d . ? g roun d pa d ?? g roun d pa d on b ottom of pa c ka g e must b e sol d ere d to main g roun d plane of p c b. table 1-1: pin descriptions (continued) pin number name timing ty p e description gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 20 of 119 fi g ure 1-1: xtal1 an d xtal2 referen c e c ir c uits 1.4 pre-programmed recognized video and graphics standards table 1-2 describes the video and graphics standards automatically recognized by the gs4911b/gs4910b. any one of th e 36 different video format s and 16 different graphic display formats listed below can be applied to the gs4911b/gs4910b and automatically detected by the reference format detector. moreover, each format, with the exception of vid_std[5:0] = 2, 52, 53, or 54, is available fo r output on the timing output pins by setting the vid_std[5:0] pins. in addition to the pre-programmed video standards listed in table 1-2 , custom output timing signals may be generated by the gs4911b/gs4910b. the custom timing parameters are programmed in the host interface when vid_std[5:0] is set to 62 (see section 3.10 on page 74 ). setting vid_std[5:0] to 63 will cause the device to produce an output format with identical timing to the detected input reference. if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video stan dard may inst ead be selected via the vid_std[5:0] register of the host interface (see section 3.12.3 on page 79 ). although the external vid_std[5:0] pins will be ignored in this case, they should not be left floating. x1 38pf x2 24pf 1m 6 7 x1 x2 6 7 nc external clock external crystal connection external clock source connection notes: 1. capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2. x1 serves as an input, which may alternatively accept a 27mhz clock source. to accomodate this, mismatched capacitor values are recommended. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 21 of 119 table 1-2: recognized video and graphics standards vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard 0p c lk1&2 =low. p c lk3/p c lk3 = hi g h impe d an c e ?????????? 14fs c 525 / 2:1 interla c e 14.32 910 525 7 6 8 6 7ne g ative 3 ne g ative 48 6s mpte 244m 2* c omposite pal 6 25 / 2:1 interla c e / 25 ?? 6 25 ? ? ne g ative 2.5 ne g ative 57 6 ? 3 6 01 525 / 2:1 interla c e 27 171 6 525 1440 127 ne g ative 3 ne g ative 48 6s mpte 125m/2 6 7m 4? 6 01 6 25 / 2:1 interla c e 27 1728 6 25 1440 127 ne g ative 2.5 ne g ative 57 6 itu-r bt. 6 01-5 5 6 01 ? 18mhz 525 / 2:1 interla c e 3 6 2288 525 1920 1 6 9ne g ative 3 ne g ative 48 6s mpte 2 6 7m 6 ? 6 01 ? 18 mhz 6 25 / 2:1 interla c e 3 6 2304 6 25 1920 1 6 9ne g ative 2.5 ne g ative 57 6 itu-r bt. 6 01-5 7 720x48 6 /59.94/2:1 interla c e 54 3432 525 2880 252 ne g ative 3 ne g ative 48 6s mpte rp174 / s mpte 347m 8? 720x57 6 /50/2:1 interla c e 54 345 66 25 2880 252 ne g ative 2.5 ne g ative 57 6 itu-r bt.799 / s mpte 347m 9 720x483/59.94/1:1 pro g ressive 54 171 6 525 1440 127 ne g ative 6 ne g ative 483 s mpte 293m / s mpte 347m 10 720x57 6 /50/1:1 pro g ressive 54 1728 6 25 1440 127 ne g ative 5 ne g ative 57 6 itu-r bt.1358 / s mpte 347m 11 1280x720/ 6 0/1:1 pro g ressive 74.25 1 6 50 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 12 1280x720/59.94/1:1 pro g ressive 74.175 1 6 50 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 22 of 119 13 1280/720/50/1:1 pro g ressive 74.25 1980 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 14 1280x720/30/1:1 pro g ressive 74.25 3300 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 15 1280x720/29.97/1:1 pro g ressive 74.175 3300 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 1 6 1280x720/25/1:1 pro g ressive 74.25 39 6 0 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 17 1280x720/24/1:1 pro g ressive 74.25 4125 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 18 1280x720/23.98/1:1 pro g ressive 74.175 4125 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 19 1920x1035/ 6 0/2:1 interla c e 74.25 2200 1125 1920 80 tri 5 ne g ative 1035 s mpte 2 6 0m 20 1920x1035/59.94/2:1 interla c e 74.175 2200 1125 1920 80 tri 5 ne g ative 1035 s mpte 2 6 0m 21 1920x1080/ 6 0/1:1 pro g ressive 148.5 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 22 1920x1080/59.94/1:1 pro g ressive 148.35 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 23 1920x1080/50/1:1 pro g ressive 148.5 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 24 reserve d ?????????? 25 1920x1080/ 6 0/2:1 interla c e 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 2 6 1920x1080/59.94/2:1 interla c e 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m table 1-2: recognized video and graphics standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 23 of 119 27 1920x1080/50/2:1 interla c e 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 28 reserve d ?????????? 29 1920x1080/30/1:1 pro g ressive 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 30 1920x1080/30/psf 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 31 1920x1080/29.97/1:1 pro g ressive 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 32 1920x1080/29.97/psf 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 33 1920x1080/25/1:1 pro g ressive 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 34 1920x1080/25/psf 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 35 1920x1080/24/1:1 pro g ressive 74.25 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 3 6 1920x1080/24/psf 74.25 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 37 1920x1080/23.98/1:1 pro g ressive 74.175 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 38 1920x1080/23.98/psf 74.175 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 39 6 40 x 480 v g a @ 6 0 hz 25.2 800 525 6 40 9 6 ne g ative 2 ne g ative 480 ibm s tan d ar d 40 6 40 x 480 v g a @ 75 hz 31.5 840 500 6 40 6 4ne g ative 3 ne g ative 480 ve s a vdmt75hz 41 6 40 x 480 v g a @ 85 hz 3 6 832 509 6 40 5 6 ne g ative 3 ne g ative 480 ve s a vdmtprop 42 800 x 6 00 s v g a @ 6 0 hz 40.00 105 66 28 800 128 positive 4 positive 6 00 ve s a v g 900 6 02 table 1-2: recognized video and graphics standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 24 of 119 43 800 x 6 00 s v g a @ 75 hz 49.5 105 66 25 800 80 positive 3 positive 6 00 ve s a vdmt75hz 44 800 x 6 00 s v g a @ 85 hz 5 6 .25 1048 6 31 800 6 4 positive 3 positive 6 00 ve s a vdmtprop 45 1024 x 7 6 8 x g a @ 6 0 hz 6 5 1344 80 6 1024 13 6 ne g ative 6 ne g ative 7 6 8ve s a v g 901101a 4 6 1024 x 7 6 8 x g a @ 75 hz 78.75 1312 800 1024 9 6 positive 3 positive 7 6 8ve s a vdmt75hz 47 1024 x 7 6 8 x g a @ 85 hz 94.5 137 6 808 1024 9 6 ne g ative 3 positive 7 6 8ve s a vdmtprop 48 1280 x 1024 s x g a @ 6 0 hz 108.00 1 6 88 10 66 1280 112 positive 3 positive 1024 ve s a vdmtrev 49 1280 x 1024 s x g a @ 75 hz 135.00 1 6 88 10 66 1280 144 ne g ative 3 positive 1024 ve s a vdmt75hz 50 1280 x 1024 s x g a @ 85 hz 157.5 1728 1072 1280 1 6 0ne g ative 3 positive 1024 ve s a vdmtprop 51? 1 6 00 x 1200 ux g a @ 6 0 hz 1 6 221 6 0 1250 1 6 00 192 ne g ative 3 positive 1200 ve s a vdmtprop 52* 1 6 00 x 1200 ux g a @ 75 hz ? ? 1250 ? ? ne g ative 3 positive 1200 ? 53* 1 6 00 x 1200 ux g a @ 85 hz ? ? 1250 ? ? ne g ative 3 positive 1200 ? 54* 2048 x 153 6 qx g a @ 6 0 hz ? ? 1589 ? ? ne g ative 3 positive 153 6 ? 55 - 6 1 reserve d ?????????? 6 2 c ustom format only ( s e c tion 3.10 on pa g e 74 ) ?????????? table 1-2: recognized video and graphics standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 25 of 119 6 3automati c output s tan d ar d follows input s tan d ar d ?????????? * vid_ s td[5:0] = 2, 52, 53, an d 54 are re c o g nize d as input referen c es only. to g enerate c lo c k an d timin g si g nals for these stan d ar d s use the d evi c e?s c ustom format c apa b ility. ? the lo c k_lo s t output si g nal will b e unsta b le when attemptin g to g enlo c k to an input referen c e c orrespon d in g to vid_ s td[5:0] = 51, althou g h the d evi c e d oes a c hieve lo c k. to c orre c t this, the user c an pro g ram re g ister a dd ress 27h = 38 d . ? when vid_ s td = 4, 6 , or 8, the v b lankin g output pulse wi d th is 2 lines too lon g for fiel d 1 an d 1 line too short for fiel d 2 when c ompare d to the d i g ital timin g d efine d in itu-r bt. 6 5 6 an d itu-r bt.799. note: 1080i/ 6 0 to v g a/ 6 0 is not a vali d lo c kin g option. table 1-2: recognized video and graphics standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 26 of 119 1.5 output timing signals table 1-3 describes the output timing signals available to the user via pins timing_out_1 to timing_out_8. the user may output any of the signals listed below on each pin by programming the output_selec t registers beginning at address 43h of the host interface. s table 1-3: output timing signals signal name description default output pin h s yn c the h s yn c si g nal has a lea d in g e dg e at the start of the horizontal syn c pulse. its len g th is d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). the wi d th of the h s yn c output pulse is d etermine d b y the sele c te d vi d eo stan d ar d . ta b le 1-2 lists the h s yn c wi d th (in c lo c ks) of ea c h pre-pro g ramme d vi d eo an d g raphi c s stan d ar d re c o g nize d b y the gs 4911b/ gs 4910b. c ustom vi d eo timin g parameters may also b e pro g ramme d in the host interfa c e to d efine a unique h s yn c wi d th (see s e c tion 3.10 on pa g e 74 ). in g enlo c k mo d e the lea d in g e dg e of the output h s yn c si g nal is nominally simultaneous with the half amplitu d e point of the referen c e h s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). by d efault, after system reset, the polarity of the h s yn c si g nal output will b e a c tive low. the polarity may b e sele c te d as a c tive hi g h b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_1 h blankin g the h blankin g si g nal is use d to in d i c ate the portion of the vi d eo line not c ontainin g a c tive vi d eo d ata. the h blankin g si g nal will b e low ( d efault polarity) for the portion of the vi d eo line c ontainin g vali d vi d eo samples. the si g nal will b e low at the first vali d pixel of the line, an d hi g h after the last vali d pixel of the line. the h blankin g si g nal remains hi g h throu g hout the horizontal b lankin g perio d . the wi d th of this si g nal will b e d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). when in g enlo c k mo d e, the output h blankin g si g nal will b e phase lo c ke d to the referen c e h s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_2 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 27 of 119 v s yn c the v s yn c timin g si g nal has a lea d in g e dg e at the start of the verti c al syn c pulse. its len g th is d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). the lea d in g e dg e of v s yn c is nominally simultaneous with the lea d in g e dg e of the first b roa d pulse. when in g enlo c k mo d e, the output v s yn c si g nal will b e phase lo c ke d to the referen c e v s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). by d efault, after system reset, the polarity of the v s yn c si g nal output will b e a c tive low. the polarity may b e sele c te d as a c tive hi g h b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_3 v blankin g the v blankin g si g nal is use d to in d i c ate the portion of the vi d eo fiel d /frame not c ontainin g a c tive vi d eo lines. the v blankin g si g nal will b e low ( d efault polarity) for the portion of the fiel d /frame c ontainin g vali d vi d eo d ata, an d will b e hi g h throu g hout the verti c al b lankin g perio d . the wi d th of this si g nal will b e d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). when in g enlo c k mo d e, the output v blankin g si g nal will b e phase lo c ke d to the referen c e v s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). note: when vid_ s td = 4, 6 , or 8, the v b lank output pulse wi d th is 2 lines too lon g for fiel d 1 an d 1 line too short for fiel d 2 when c ompare d to the d i g ital timin g d efine d in itu-r bt. 6 5 6 an d itu-r bt.799. timin g _out_4 f s yn c the f s yn c si g nal is use d to in d i c ate fiel d 1 an d fiel d 2 for interla c e d vi d eo formats. the f s yn c si g nal will b e hi g h ( d efault polarity) for the entire perio d of fiel d 1. it will b e low for all lines in fiel d 2 an d for all lines in pro g ressive s c an systems. the wi d th an d timin g of this si g nal will b e d etermine d b y the v s yn c parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom v s yn c timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). the f s yn c si g nal always c han g es state on the lea d in g e dg e of v s yn c . when in g enlo c k mo d e, the output f s yn c si g nal will b e phase lo c ke d to the referen c e f s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_5 table 1-3: output timing signals (continued) signal name description default output pin gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 28 of 119 f di g ital f di g ital is use d in d i g ital interla c e d stan d ar d s to in d i c ate fiel d 1 an d fiel d 2. the f di g ital c han g es state at the lea d in g e dg e of every v blankin g pulse. it will b e low ( d efault polarity) for the entire perio d of fiel d 1 an d for all lines in pro g ressive s c an systems. it will b e hi g h for all lines in fiel d 2. the wi d th an d timin g of this si g nal will b e d etermine d b y the timin g parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). when in g enlo c k mo d e, the output f di g ital si g nal will b e phase lo c ke d to the referen c e f s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 38 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_ 6 10 fiel d i d entifi c ation the 10 fiel d i d entifi c ation (10fid) si g nal is use d to in d i c ate the 10-fiel d sequen c e for 29.97hz, 30hz, 59.94hz an d 6 0hz vi d eo stan d ar d s. it will b e low for output stan d ar d s with other frame rates. the sequen c e d efines the phase relationship b etween film frames an d vi d eo frames, so that c a d en c e may b e maintaine d in mixe d format environments. the 10fid si g nal will b e hi g h ( d efault polarity) for one line at the start of the 10-fiel d sequen c e. it will b e low for all other lines. the si g nal?s risin g an d fallin g e dg es will b e simultaneous with the lea d in g e dg e of the h s yn c output si g nal. alternatively, b y settin g b it 4 of the vi d eo_ c ontrol re g ister (see s e c tion 3.12.3 on pa g e 79 ), the 10fid output si g nal may b e c onfi g ure d to g o hi g h ( d efault polarity) on the lea d in g e dg e of the h s yn c output on line 1 of the first fiel d in the 10 fiel d sequen c e, an d b e reset low on the lea d in g e dg e of the h s yn c pulse of the first line of the se c on d fiel d in the 10 fiel d sequen c e. when in g enlo c k mo d e, the output 10fid si g nal will b e phase lo c ke d to the 10fid referen c e input. if a 10fid input is not provi d e d to the d evi c e, the user must c onfi g ure the 10fid output usin g re g ister 1ah of the host interfa c e (see s e c tion 3.8.1 on pa g e 6 7 ). for appli c ations involvin g au d io, this si g nal may b e use d in pla c e of the af s si g nal if the format sele c te d is appropriate for a 10 fiel d af s repetition rate, an d the d esire d phase relationship of au d io to vi d eo c lo c k phasin g c oin c i d es with the d esire d film frame c a d en c e. the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). please see s e c tion 3.8.1 on pa g e 6 7 for more d etail on the 10fid output si g nal. timin g _out_7 table 1-3: output timing signals (continued) signal name description default output pin gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 29 of 119 display ena b le the display ena b le (de) si g nal is use d to in d i c ate the d isplay ena b le for g raphi c d isplay interfa c es. this si g nal will b e hi g h ( d efault polarity) whenever pixel information is to b e d isplaye d on the d isplay d evi c e (i.e. whenever b oth h blankin g an d v blankin g are in the a c tive vi d eo state) the wi d th an d timin g of this si g nal will b e d etermine d b y the timin g parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ), or a cc or d in g to c ustom timin g parameters pro g ramme d in the host interfa c e (see s e c tion 3.10 on pa g e 74 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). timin g _out_8 au d io frame s yn c ( gs 4911b only) the au d io frame s yn c (af s ) si g nal is hi g h ( d efault polarity) for the d uration of the first line of the n?th vi d eo frame to in d i c ate that the a c lk d ivi d ers are reset at the start of line 1 of that frame. it is d efine d a cc or d in g to the frame rate of the vi d eo format an d the sele c te d au d io sample rate pro g ramme d via the vid_ s td[5:0] an d a s r_ s el[2:0] pins or the host interfa c e. for example, if the vi d eo format is b ase d on a 59.94hz frame rate an d the au d io sample rate c lo c k is 48khz, then n=5, an d the af s si g nal will b e i d enti c al to the 10fid si g nal. by d efault, the af s si g nal is reset b y the 10 fiel d i d entifi c ation (10fid) referen c e input. this feature may b e d isa b le d usin g the au d io_ c ontrol re g ister at a dd ress 31h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). the af s si g nal may also b e reset usin g re g ister 1ah of the host interfa c e. with no referen c e, the frame d ivi d e b y ?n? c ontrollin g the af s si g nal will free-run at an ar b itrary phase. the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.12.3 ). please see s e c tion 3.8.2 on pa g e 6 8 for more d etail on the af s output si g nal. ? u s er_1~4 the gs 4911b/ gs 4910b offers four user pro g ramma b le output si g nals. ea c h u s er si g nal is c ontrolle d b y four timin g re g isters an d a polarity sele c t b it. the timin g re g isters d efine the start an d stop times in h pixels an d v lines an d b e g in at a dd ress 57h of the host interfa c e (see s e c tion 3.12.3 on pa g e 79 ). ea c h user si g nal is in d ivi d ually pro g ramma b le an d the polarity, position, an d wi d th of ea c h output may b e d efine d with respe c t to the h, v, an d f output timin g s of the d evi c e. ea c h output si g nal may b e pro g ramme d in b oth the horizontal an d verti c al d imensions relative to the lea d in g e dg es of h an d v s yn c . if d esire d , the pulses pro d u c e d may then b e c om b ine d with a lo g i c al and, or, or xor fun c tion to pro d u c e a c omposite si g nal (for example, a horizontal b a c k por c h pulse d urin g a c tive lines only, or the a c tive part of lines 15 throu g h 20 for verti c al information retrieval). ea c h output has sele c ta b le polarity. please see s e c tion 3.8.3 on pa g e 6 9 for more d etail on the u s er_1~4 output si g nals. ? table 1-3: output timing signals (continued) signal name description default output pin gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 30 of 119 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter conditions value/units s upply volta g e c ore an d analo g ( c ore_vdd, vid_pll_vdd, aud_pll_vdd, ph s _vdd, analo g _vdd) ? -0.3v to +2.1v s upply volta g e i/o (io_vdd, xtal_vdd) ? -0.3v to +3. 6 v input volta g e ran g e (any input) io_vdd = +3.3v -0.3v to +5.5v io_vdd = +1.8v -0.3v to +3. 6 v operatin g temperature ? -20 c < t a < 85 c s tora g e temperature ? -50 c < t s t g < 125 c s ol d erin g temperature ? 2 6 0 c e s d prote c tion on all pins ? 1 kv table 2-1: dc electrical characteristics v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes system operatin g temperature ran g et a ? 0 25 70 c 1 c ore power supply volta g e c ore_vdd ? 1.71 1.8 1.89 v ? di g ital i/o buffer power s upply volta g e io_vdd 1.8v operation 1.71 1.8 1.89 v ? io_vdd 3.3v operation 3.135 3.3 3.4 6 5v ? vi d eo pll power s upply volta g e vid_pll_vdd ? 1.71 1.8 1.89 v ? au d io pll power s upply volta g e ( gs 4911b only) aud_pll_vdd ? 1.71 1.8 1.89 v ? analo g power s upply volta g e analo g _vdd ? 1.71 1.8 1.89 v ? c rystal buffer power s upply volta g e xtal_vdd 1.8v operation 1.71 1.8 1.89 v ? xtal_vdd 3.3v operation 3.135 3.3 3.4 6 5v ? vi d eo c lo c k phase s hift s upply volta g e ph s _vdd ? 1.71 1.8 1.89 v ? gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 31 of 119 s ystem power p d gs 4911b c ore_vdd = max io_vdd = max t = 70 o c unloa d e d , max p c lk frequen c y ??450mw? p d gs 4911b c ore_vdd = 1.8v io_vdd = 3.3v t = 25 o c unloa d e d , p c lk = 74.25mhz ?300?mw? p d gs 4910b c ore_vdd = max io_vdd = max t = 70 o c unloa d e d , max p c lk frequen c y ??400mw? p d gs 4910b c ore_vdd = 1.8v io_vdd = 3.3v t = 25 o c unloa d e d , p c lk = 74.25mhz ?250?mw? digital i/o input volta g e, lo g i c low v il 1.8v operation ? ? 0.35 x vdd v? v il 3.3v operation ? ? 0.8 v ? input volta g e, lo g i c hi g hv ih 1.8v operation 0. 6 5 x io_vdd ?3. 6 v? v ih 3.3v operation 2.145 ? 5.25 v ? output volta g e, lo g i c low v ol c urrent d rive = hi g h or low as sele c te d ??0.4v2 output volta g e, lo g i c hi g hv oh c urrent d rive = hi g h or low as sele c te d 0. 6 5 x io_vdd ??v 2 supply pin current requirements vid_pll_vdd (1.9v) ? ? ? ? 28.50 ma ? xtal_vdd (3. 6 v) ? ? ? ? 1.71 ma ? aud_pll_vdd (1.9v) ? ? ? ? 31.45 ma ? io_vdd (3. 6 v) ? ? ? ? 6 .80 ma ? table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 32 of 119 c ore_vdd (1.9v) ? ? ? ? 42.45 ma ? lvd s /p c lk3_vdd (1.9v) ? ? ? ? 6 .32 ma ? p c lk1&2_vdd (1.9v) ? ? ? ? 22.24 ma ? analo g _vdd (1.9v) ? ? ? ? 3.94 ma ? ph s _vdd (1.9v) ? ? ? ? 11.54 ma ? digital output currents timin g output drive c urrent ? io_vdd = 1.8v c urrent d rive = low ?5?ma? ? io_vdd = 3.3v c urrent d rive = low ?10?ma? ? io_vdd = 1.8v c urrent d rive = hi g h ?7?ma? ? io_vdd = 3.3v c urrent d rive = hi g h ?14?ma? c lo c k output drive c urrent ? io_vdd = 1.8v c urrent d rive = low ?5?ma? ? io_vdd = 3.3v c urrent d rive = low ?7?ma? ? io_vdd = 1.8v c urrent d rive = hi g h ?7?ma? ? io_vdd = 3.3v c urrent d rive = hi g h ?14?ma? output volta g e lvd s , c ommon mo d e v o c m ? 1.125 1.25 1.375 v 3 output volta g e lvd s , differential v odiff ??350?mv3 lvd s hi g h-impe d an c e leaka g e c urrent ? to 1.8v or g nd ? ? 1.4 ua ? note s 1. all dc and ac electrical parameters within specification. 2. assuming that the current being sourced or sinked is less than the timing output drive current specified. 3. into a 100 termination connected between pclk3 and pclk3 . table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 33 of 119 2.3 ac electrical characteristics table 2-2: ac electrical characteristics v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes system referen c e dete c tion time ? from when the referen c e input is first present ? 2 4 frames ? digital i/o p c lk output frequen c y ? ? 3.375 ? 1 6 5mhz? p c lk j itter ? s d vi d eo stan d ar d s xtal_vdd = 3.3v ? 350 ? ps 1, 2 ? hd & g raphi c s vi d eo stan d ar d s xtal_vdd = 3.3v ? 250 ? ps 1, 3 p c lk duty c y c le ? ? 40 ? 6 0%? p c lk1 & p c lk2 rise/fall times 15pf loa d 20% - 80% ? io_vdd = 1.8v c urrent d rive = low ??1.7ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??1.1ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??0.9ns? p c lk3 rise/fall time 20% - 80% ? 100 d ifferential loa d 10pf to g roun d per pin ? ? 850 ps ? p c lk outputs relative timin g s kew ? d efault p c lk phase d elay of zero -3 ? 3 ns 4 a c lk frequen c y ( gs 4911b only) ? ? 0.0097 ? 49.152 mhz ? a c lk duty c y c le ( gs 4911b only) ?? 40? 6 0%5 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 34 of 119 a c lk1-3 rise/fall times 15pf loa d 20% - 80% ( gs 4911b only) ? io_vdd = 1.8v c urrent d rive = low ??3.0ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??2.5ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??1.4ns? a c lk outputs relative timin g s kew ( gs 4911b only) ?? -3?3ns4 di g ital timin g output delay time t od ???4.3ns 6 di g ital timin g output hol d time t oh ?1??ns 6 di g ital timin g output rise/fall times 15pf loa d 20% - 80% ? io_vdd = 1.8v c urrent d rive = low ??3.0ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??2.5ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??1.4ns? gspi gs pi input c lo c k frequen c yf gs pi ? ? ? 10.0 mhz 7 gs pi c lo c k duty c y c le d c gs pi ?40? 6 0%7 gs pi input s etup time t 3 in fi g ure 3-18 ?1.5??ns7 table 2-2: ac electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 35 of 119 gs pi input hol d time t 8 in fi g ure 3-18 ?1.5??ns7 note s 1. the video output clock may be directly connected to gennums gs1532 or gs1531 serializer for a smpte-compliant sdi or hd-sdi output with output jitter below 0.2ui, when the serializer is configured for a loop bandwidth of 100khz. 2. all sd standards except vid_std[5:0] = 1 (450 ps typ.) and vid_std[5:0] = 5 or 6 (500ps typ.) 3. all hd and graphics standards exc ept vid_std[5:0] = 22 (300ps typ.) and vid_std[5:0] = 41-43 (400ps typ.) 4. timings from any clk output to any other clk output. 5. if fs=96khz and aclk is configured to output a clock signal at 192fs or 384fs, a 512f s clock will typicall y have a 33% duty c ycle distortion. see section 3.7.2 on page 63 . 6. with pclk phasing delay set to nominal (zero offset), each increment of the clock phasing ad justment decreases output hold ti me and delay time by a nominal 700ps. the times t od and t oh are defined in figure 2-1 . 7. for detailed gspi timing parameters, please refer to table 3-12 . table 2-2: ac electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 36 of 119 fi g ure 2-1: p c lk to timin g _out s i g nal output timin g table 2-3: suggested external crystal specification 27.000000 mhz at c ut nominal dissipation = 50 uw frequen c y a cc ura c y at 25 c = +/- 10ppm frequen c y variation 0-70 c = +/- 10ppm a s r = 50 +/- 20 note: the user may sele c t an appropriate c rystal a cc ura c y for their appli c ation. if the d evi c e is operatin g in free run mo d e, the output c lo c k an d timin g si g nals will have the same a cc ura c y as the c rystal. however, if operatin g in g enlo c k mo d e, all output si g nals are b ase d on the input referen c e, an d therefore a less a cc urate c rystal may b e suffi c ient. s ee s e c tion 3.2 on pa g e 37 . 50 % t oh t od v oh v ol v oh v ol timing_out pclk gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 37 of 119 3. detailed description 3.1 functional overview the gs4911b/gs4910b is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. the device has two main modes of operation: genlock mode and free run mode. in genlock mode, the video clock and timing outputs, will be frequency and phase locked to the detected reference input signal. in free run mode, the occurrence of all frequencies is based on a 27mhz external crystal reference. the gs4911b/gs4910b will recognize input re ference signals conforming to 36 different video standards and 16 different graphic formats. it supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. when the device is in genlock mode and the input reference is removed, the gs4911b/gs4910b will enter freeze mode. in this mode, the output clock and timing signals will maintain their previously genlocked phase and frequency to within +/- 2ppm. the user may select to output one of 8 different video sample clock rates or 13 different graphic display clock rates, or may program any clock fr equency between 13.5mhz and 165mhz. the chosen clock frequency may be furt her internally divided, and is available on two video clock outputs and one lvds video clock output pair. the video clocks may also be individually phase delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 35 different video formats and 13 di fferent graphics formats: hsync, hblanking, vsync, vblanking, f sync, f digital, afs (gs4911b only), de, and 10fid. alternatively, custom output timing signals may be programmed in the host interface. in addition, the gs4911b provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging fr om 9.7khz to 96khz. audio to video phasing is accomplished by either an external 10fid input reference, a 10fid signal specified via internal registers, or a user-programmed audio frame sequence. 3.2 modes of operation the gs4911b/gs4910b will operate in either genlock mode or free run mode depending on the setting of the genlock pin. these two modes are described in section 3.2.1 on page 38 and section 3.2.2 on page 41 respectively. if desired, the external genlock pin may be ignored by setting bit 5 of the genlock_control register (address 16h) so that genlock can instead be controlled via the host interface (see section 3.12.3 on page 79 ). although the external genlock pin will be ignored in this case, it should not be left floating. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 38 of 119 3.2.1 genlock mode when the application layer sets the genlock pin low and the device has successfully genlocked the outputs to th e input reference, the gs491 1b/gs4910b will enter genlock mode. in this mode, all clock and timing generator outputs will be frequency and phase locked to the detected input reference signal. the pclk outputs will be locked to the h reference. when in genlock mode, the output clock and timing signals are generated using the applied reference signal. the 27mhz crysta l reference is necessary for operation; however, neither crystal accuracy nor changes in crystal frequency (due to a shift in operating temperature) will affect the output signals. for example, the output signals will be generated with the same accuracy whether the 27mhz reference crystal has an accuracy of 10ppm or 100ppm. the gs4911b/gs4910b suppor ts cross-locking, allowing th e outputs to be genlocked to an incoming reference that is different from the output video standard selected (see section 3.6 on page 50 ). note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. 3.2.1.1 genlock timing offset by default, the phase of the clock and timing out signals is genlocked to the input reference signal. these output signals may be phase adjusted with respect to the input reference by programming the host interface (see section 3.12.3 on page 79 ). offsets are separately programmable in terms of clock ph ase, horizontal phase, and vertical phase (i.e. fractions of a pixel, pixels, and lines). genlock timing offsets can be used to co-time the output of a piece of equipment containing the gs4911b/gs4910b with the ou tputs of other equi pment at different locations. the signal leaving the piece of equipment containing the gs4911b/gs4910b may pass through processing equipment with significant fixed delays before arriving at the switcher. these delays may include video line delays or even field delays. to compensate for these delays, genlock timing offsets allow the user to back-time the output of the equipment relative to the input reference. using the host interface, the following regist ers may be programmed once the device is stably locked: ? clock_phase_offset (1dh) - with a range of zero to one clock pulse in increments of between 1/64 and 1/512 of a clock period (d epending on the pclk frequency). the increments will be between 100ps and 200ps . all clock and timing output signals will be delayed by the clock phase o ffset programmed in this register. ? h_offset (1bh) - the difference between the reference hsync signal and the output h sync and/or h blanking signal in clock pu lses, with a control range of zero to +1 line. all timing output signals will be delayed by the horizontal offset programmed in this register. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 39 of 119 ? v_offset (1ch) - the difference between th e reference vsync signal and the output v sync and/or v blanking in lines, with a control range of zero to +1 frame. all line-based timing output signals will be delayed by the vertical offset programmed in this register. the encoding scheme for the clock_phase_offset register (1dh) is shown in table 3-1 . the offset programmed will be in the positive direction. note that the step size will depend on the frequency of the output video clock. note: if vid_std[5:0] = 63 and the reference fo rmat is changed, care must be taken to ensure that the clock_phase_offset register is correctly programmed for the new output format before the reference is applied. the value programmed in the h_offset regi ster (1bh) must not exceed the maximum number of clock periods per line of the outgoing video standard. similarly, the value programmed in the v_offset register (1ch) must not exceed the maximum number of lines per frame of the outgoing standard. both horizontal and vertical offsets will be in the positive direction. negative offsets (adv ances) are achieved by programming a value in the appropriate register equal to the maximum allowable offset minus the desired advance. notes: 1. the device will delay all output timing signals by 2 pclks relative to the input hsync reference. this will occur even when the h_offset register is not programmed. the user may compensate for th is delay by subtracting 2 pclk cycles from the desired horizontal offset before loading the value into the host interface. table 3-1: clock_phase_offset[15:0] encoding scheme vid_std[5:0] setting output video clock frequency step size (fraction of a pclk) maximum number of steps bits required to set the number of steps clock_phase_offset [15:0] settings 1 f p c lk < 20mhz 511 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 8 000001 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 3- 6 , 39-42 20mhz < f p c lk < 40mhz 255 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 000010 b 7 b 6 b 5 b 4 0 b 3 b 2 b 1 b 0 7-20, 25-38, 43-4 6 40mhz < f p c lk < 80mhz 127 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 6 000100 b 6 b 5 b 4 00 b 3 b 2 b 1 b 0 21-23, 47-51 f p c lk > 80mhz 6 3 b 5 b 4 b 3 b 2 b 1 b 0 b 5 001000 b 5 b 4 000 b 3 b 2 b 1 b 0 note: pro g ram c lo c k_phase_offset = 0000 0000 0000 0000 b to a c hieve a zero c lo c k phase offset. 1 512 -------- - 1 256 -------- - 1 128 -------- - 1 64 ----- - gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 40 of 119 2. for both sync and blanking-based input references, the device will advance all line-based output timing signals by 1 line relative to the input vsync reference for all output standards except vid_std[5:0] = 4, 6, and 8. this will occur even when the v_offset register is not programmed. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. 3. when locking the ? f/1.001 ? hd output standards to th e 525-line sd input reference standards, or vice versa, the device will delay all line-based output timing signals by vsync lines relative to the input vsync reference. this will occur even when the v_offset register is not programmed. the user may compensate for this delay by subtracting vsync lines from the desired vertic al offset before loading this value into the register. the value vsync is given by the equation: where: hsync_in_period = the period of the h reference pulse vsync_hsync = the time difference between the leading edges of the applied v and h reference pulses hsync_out_period = the period of the generated h sync output see figure 3-1 . h_feedback_divide represents the numerator of the ratio of the output clock frequency to the frequency of the h reference pulse. it is calculated as described in section 3.6.2.1 on page 54 . fi g ure 3-1: hd- s d c al c ulation vsync hsync_in_period vsync _hsync 2 ( hsync_out_period ) ? + = h s yn c v s yn c h s yn c v s yn c d v s yn c _h s yn c h s yn c _out_perio d h s yn c _in_perio d d v s yn c gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 41 of 119 4. for sync-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the h_offset register is greater than 20. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. in addition, the internal v_lock and f_lock signals repo rted in bits 3 and 4 of register 16h will be low when h_offset = 20 only, although the device will remained genloc ked. the user may choose to mask these lock signals such that the device will continue to report genlock under this condition. 5. for blanking-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the h_offset register is greater than the number of output video clock cycles from the start of h sync to the end of active video (hsync_to_eav) + 20. the va lue of hsync_to_eav is reported in register 51h and changes according to th e output vid_std selected. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. in addition, the internal v_lock and f_lock signals reported in bits 3 and 4 of regi ster 16h will be low when h_offset = hsync_to_eav + 20 only, although the devi ce will remained ge nlocked. the user may choose to mask these lock signals such that the device will continue to report genlock under this condition. 6. the offsets that occur as described in notes 1-5 are independent of one another and must be accounted for as such. 3.2.1.2 freeze mode when the device is in genlock mode and the input reference is removed, the gs4911b/gs4910b will enter freeze mode. the behaviour of the device during loss and re-acquisition of an input reference signal is described in section 3.5.3 on page 47 . in freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm. this assumes a loop bandwidth of 10hz. also, if the frequency of the 27mhz reference crystal shifts while in freeze mode, the frequency of the output clock and timing signals will shift as well. 3.2.2 free run mode the gs4911b/gs4910b will enter free run mode when the genlock pin is set high by the application layer. in this mode, the oc currence of all frequencies is based on the external 27mhz reference input. therefore, the frequency of the output clock and timing signals will have the same accuracy as the crystal reference. if operating in free run mode, using a more accurate crystal (e.g. 10ppm) ensures more accurate clock and timing signals are generated. note: in free run mode, the audio clocks of the gs4911b will remain genlocked to the video clock. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 42 of 119 figure 3-2 summarizes the differences in output accuracy in each mode of operation. assuming a crystal reference of +/-100ppm, in free run mode the frequency of the output clock and timing signals will be as accurate as the crystal. in genlock mode the frequency will be as accurate as the input reference regardless of the crystal accuracy. in freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm. fi g ure 3-2: output a cc ura c y an d mo d es of operation 3.3 output timing format selection at device power-up (described in section 3.14 on page 111 ), the application layer should immediately set the external vid_std[5:0] and asr_sel[2:0] pins. the vid_std[5:0] pins are used to select a pre-programmed output video format, or to indicate that custom timing parameters will be programmed in the host interface. the asr_sel[2:0] pins are only available on the gs4911b , and are used to select the fundamen tal audio frequency or to turn off audio clock generation. the output timing formats selectable by the us er via the vid_std[5:0] pins are listed in section 1.4 on page 20 . table 3-7 in section 3.7.2 on page 63 lists the audio sample rates available via the asr_sel[2:0] pins. if the user sets vid_std[5:0] =1-51 on power-up, the device will first check the status of the genlock pin. if genlock is set low and a valid reference has been applied to the inputs, the device will output the selected video standard while attempting to genlock. however, if a reference signal has not been applied and genlock =low, the initial clock and timing outputs may be determined by the internal default settings of the chip. if genlock is set high, the device will immediately enter free run mode and will correctly output the selected video standard. if the user sets vid_std[5:0] = 62 on power-up , the device will be configured to generate custom output timing signals. the initial output timing signals will be equal to the internal default timing of the chip until the user programs registers 4eh to 55h of the host interface (see section 3.10 on page 74 ). additionally, the output video clock will run at a free run genlock freeze 74.25 mhz -2ppm no input reference reference applied reference lost time assumption: reference xtal is 27mhz+/-100ppm -100ppm +100ppm +2ppm + notes: 1. t represents the temperature variability of the crystal 2. diagram not to scale. t t - t + t - t gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 43 of 119 frequency determined by the internal default settings of the chip until the user modifies it via registers 20h to 23h (see section 3.9.1 on page 72 ). if the user sets vid_std[5:0] = 63 on power-up, the device will wait until a valid reference has been applied, at which time it will output the same video format as the input reference and enter genlock mode if genlock = low. when operating in fr ee run or genlock mode, the gs 4911b/gs4910b will continuously monitor the settings of the vid_std[5:0] and asr_sel[2:0] pins. if the user wishes to change the format of the output clocks and timing signals, these pins may be reconfigured at any time, although it is recommended that the device be reset when changing output video standards. 3.4 input reference signals the hsync, vsync, fsync, and 10fid reference signals are applied to the gs4911b/gs4910b via the de signated in put pins. to operate in genlock mode, the input reference signals must be valid and must conform to a recognized video or graphics standard (see section 3.5 on page 45 ). alternatively, if vid_std[5:0] = 62, the signal applied to the hsync input must be stable and have a period of less than 2.4ms. in free run mode, no input reference is required. section 3.4.1 on page 43 describes the hsync, vsync and fsync input timing. the 10fid input signal is discussed in section 3.4.2 on page 44 . 3.4.1 hsync, vsync, and fsync timing for video formats the hsync, vsync, and fsync input referenc e signals may have analog timing, such as from gennum?s gs4981/ 82 sync separators ( figure 3-3 ), or may have digital timing, such as from gennum?s gs1559/60a/61 deserializers ( figure 3-4 ). section 1.4 on page 20 lists the 36 pre-programmed video timing formats recognized by the gs4911b/gs4910b. if the input reference format does not include an f sync signal, the fsync pin should be held low. fi g ure 3-3: example h s yn c , v s yn c , an d f s yn c analo g input timin g from a s yn c s eparator hsync vsync fsync gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 44 of 119 fi g ure 3-4: example h blankin g , v blankin g , an d f di g ital input timin g from an s di deserializer timing for graphics formats the gs4911b/gs4910b is pre-pr ogrammed to recognize th e timing for 16 different graphics formats presented to the input reference pins. these graphic formats are described in section 1.4 on page 20 . the supported graphics standards are all progressive, and do not use the fsync signal. therefore, fsync should be held low by the application layer. the vesa formats supported have a 0.5% frequency tolerance. vsync transitions are typically co-timed with the leading edge of hsync. the duration and polarity of these signals for each format is listed in table 1-2 . note: the user must ensure that the inpu t hsync polarity for vid_std [5:0] = 47 and 49 ? 54 be active low. 3.4.2 10fid the 10fid input is a reset pin, which can be used to reset the divider for the 10fid output signal. in the gs4911b, the 10fid input pin will also reset the divider for the afs output signal. this default setting may be modified using the audio_control register of the host interface (see section 3.12.3 on page 79 ). the gs4911b will reset the phase of the audio cl ocks to the leading edge of the h sync output on line 1 of every output frame in which the 10fid input is high. this enables the user to reset the phase of the dividers when generating custom signals via the host interface (see section 3.7.2.1 on page 65 ). if the input reference format does not include a 10 field id signal, the external 10fid input pin should be held low. the timing of the 10fid input signal is shown in figure 3-5 . h:v:f timing - hd 20-bit output mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff xyz (eav) xyz (sav) xyz (sav) h signal timing typical h timing alternative h timing gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 45 of 119 fi g ure 3-5: 10fid input timin g 3.4.3 automatic po larity recognition to accommodate any standards that employ the polarity of the h and v sync signals to indicate the format of the display, the gs4911b/gs4910b will recognize h and v sync polarity and automatically synchronize to the leading edge. the polarities of the hsync and vsync signals are reported in bits 3 and 4 of the video_status register. additionally, bit 2 of this register reports the detection of either analog or digital input timing. see section 3.12.3 on page 79 for detailed register descriptions. 3.5 reference format detector the reference format detector checks the validity and analyzes the format of the input reference signal. it is designed to accurately differentiate between 59.94 and 60hz frame rates. 3.5.1 horizontal and vertical ti ming characteris tic measurements when a reference signal is applied to the desi gnated input pins, the gs4911b/gs4910b will analyse the signal and report the following in registers 0ah to 0eh of the host interface: ? the number of 27mhz clock pulses between leading edges of the h input reference signal (h_period register) ? the number of 27mhz clock pulses in 16 horizontal periods (h _16_period register) ? the number of h reference pulses between leading edges of the v input reference signal (v_lines register) ? the number of h reference pulses in two vertical periods (v_2_lines register) ? the number of h reference pulses in one f period (f_lines register) these parameters may be read via the host interface and are used by the device to determine reference signal validity. 10fid input horizontal sync input total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 46 of 119 3.5.2 input reference validity before the device attempts to operate in genlock mode, the input signals applied to hsync and vsync must be valid and must co nform to one of the 36 recognized video standards or 16 recognized grap hics standards described in section 1.4 on page 20 . alternatively, if vid_std[5:0] = 62, the device may be manually programmed to genlock to a reference that is neither valid nor recognized (see section 3.10.1 on page 75 ). for an input reference signal to be considered valid, the periodicity of hsync must be between 9us and 70us, and the periodicity of vsync must be between 8ms and 50ms. the fsync signal is not essential for validity. for output video standards other than vid_std[5:0] = 62, the ref_lost pin will be set low once the input reference signal is considered valid. if the input signal is valid, the device then compares the timing parameters of the input reference signal to each of the 36 vide o and 16 graphics standards listed in table 1-2 , and determines if the input reference is one of the recognized standards. if it is, the vid_std[5:0] value for the format is written to the input_standard register at address 0fh of the host interface. if the input signal is invalid, or if the reference format is unrecognized, 00h is programmed in this register. once a reference signal is valid and recogn ized by the device, vsync and fsync will no longer be monitored. loss of signal on these pins will not affect the operation of the device. if vid_std[5:0] is not set to 62 and the ref_lost pin is high, or if the input signal is valid, but unrecognized as one of the 36 video or 16 graphics formats, the genlock pin should not be set low. if vid_std[5:0] = 62, the ref_lost output wi ll reflect the presence of a stable signal with a period of less than 2.4ms on the hsync input pin. this allows the user to program the device to lock to a single input reference only the ref_lost output pin may also be read via bit 0 of the genlock_status register (see section 3.12.3 on page 79 ). 3.5.2.1 ambiguous standard selection there are some standards with identical h, v, and f timing parameters, such that the gs4911b/gs4910b?s reference fo rmat detector ca nnot distinguis h between them. table 3-2 groups standards with shared h, v, and f periods. us ing the amb_std_sel register at address 10h of the host interface, the user may select their choice of standard to be identified with a particular set of measurements. for exampl e, to have 1716 clocks of 27mhz per line with 525 lines per frame identified as 4fsc 525, program amb_std_sel[10:0] = xxx10xxxxxx, wher e ?x? signifies ?don?t care?. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 47 of 119 3.5.3 behaviour on loss and re-acq uisition of the reference signal by default, the gs4911b/gs 4910b will ignore one missing h pulse on the hsync pin and will continue to operate in genlock mode (although the lock_lost pin will temporarily be set high). this behaviour is controlled by the run_window bits of register address 24h. if there are two consecutive missing h pulses on the hsync input pin, the ref_lost and lock_lost pins will both go high and the device will enter freeze mode. an internal flywheel ensures the selected output clock and timing signals maintain their previous phase and frequency and continue to operate without glitches. the vsync and fsync signals are not monitored in genlock mode; loss of signal on these pins will not affect the operation of the device. table 3-2: ambiguous standard identification number standard h (27mhz clocks) 16_h (27mhz clocks) v (lines) f (lines) amb_std_sel[10:0] 1 1920x1080/ 6 0/2:1 interla c e 800 12800 5 6 2.5 1125 x x x x x x x x x 0 0 1920x1080/30/psf 800 12800 5 6 2.5 1125 x x x x x x x x x 0 1 1920x1035/ 6 0/2:1 interla c e 800 12800 5 6 2.5 1125 x x x x x x x x x 1 0 2 1920x1080/59.94/2:1 interla c e 800.8 12813 5 6 2.5 1125 x x x x x x x 0 0 x x 1920x1080/29.97/psf 800.8 12813 5 6 2.5 1125 x x x x x x x 0 1 x x 1920x1035/59.94/2:1 interla c e 800.8 12813 5 6 2.5 1125 x x x x x x x 1 0 x x 3 1920x1080/50/2:1 interla c e9 6 0 153 6 05 6 2.4 1125 x x x x x 0 0 x x x x 1920x1080/25/psf 9 6 0 153 6 05 6 2.4 1125 x x x x x 0 1 x x x x 4 6 01 525 / 2:1 interla c e 171 6 2745 6 2 6 2.5 525 x x x 0 0 x x x x x x 720x48 6 /59.94/2:1 interla c e 171 6 2745 6 2 6 2.5 525 x x x 0 1 x x x x x x 4fs c 525 / 2:1 interla c e 171 6 2745 6 2 6 2.5 525 x x x 1 0 x x x x x x 6 01 - 18mhz 525/2:1 interla c e 171 6 2745 6 2 6 2.5 525 x x x 1 1 x x x x x x 5 6 01 6 25 / 2:1 interla c e 1728 27 6 48 312.5 6 25 x 0 0 x x x x x x x x 720x57 6 /50/2:1 interla c e 1728 27 6 48 312.5 6 25 x 0 1 x x x x x x x x c omposite pal 6 25/2:1/25 1728 27 6 48 312.5 6 25 x 1 0 x x x x x x x x 6 01 - 18mhz 6 25/2:1 interla c e 1728 27 6 48 312.5 6 25 x 1 1 x x x x x x x x 66 40 x 480 v g a @ 6 0hz 857.14 13714 525 525 0 x x x x x x x x x x 720x483/59.94/1:1 pro g ressive 858 13728 525 525 1 x x x x x x x x x x note: ?x? si g nifies ? d on?t c are.? the x b it will b e i g nore d when d eterminin g whi c h stan d ar d to sele c t in ea c h of the 6 g roups a b ove. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 48 of 119 note 1: if the input reference is removed an d re-applied, all line-based timing outputs will be inaccurate for up to one frame for all output standards. note 2: when locking the ?f/1.001? hd output standards to the sd input reference standards 3, 5, 7, or 9, or vice versa, there may be a random phase difference between the input vsync and output v sync signals oc curring each time the input reference is removed and re-applied. this wi ll affect all line-based timi ng outputs. for cases where the user must manually video genlock the device, the problem will occur whenever the value programmed for h_reference_divide (registers 2b-2a h ) is greater than 1. the user may reset the line-based counters after the reference is re-applied without disrupting the pixel or audio clocks by to ggling bit 15 of register addres s 83h in the host interface. this will cause the input vsync and line-based timing output signals to take on their default timing relationship, as described in note 3 of section 3.2.1.1 on page 38 . re-acquisition of the same reference upon re-application of the reference signal, the device checks whether the reference has drifted more than +/- 2us from its expected location by comparing the current relative position of the h pulses with the previous position, over a 16-line interval. if the reference returns with the h pulses in the ex pected location +/- 2us, the pll will drift lock and the clock generator will continue to operate without a glitch. the ref_lost and lock_lost pins will be set back low. if the reference returns with the h pulses outside the +/- 2us window, the device will crash lock the output timing to the new input phase. the principles of crash lock and drift lock are described in section 3.6.3 on page 58 . note: to resume proper genlock operation upon re-application of the reference signal, the user must implement the following register manipulation every time the reference is removed and re-applied: 1. read the value containe d in register address 24h 2. clear the run_window bi ts [2:0] of register 24h 3. re-write the value read in st ep 1 to register address 24h. this procedure will force the device to lock to the reference as described above, but will maintain the flywheeling capa bility of the gs4911b/gs4910b should a single missing h pulse occur in the genlocked state. to avoid the above procedure, the user may choose to clear the run_window bits [2:0] of register address 24h upon power-up or reset. however, this will disable the flywheeling feature of the device that allows it to maintain genlock through one missing input h pulse. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 49 of 119 acquisition of a new reference when a new reference is applied, the device continues to operate in freeze mode while the reference format detector chec ks for validity as described in section 3.5.2 on page 46 . once validity is detected, the ref_lost pin is set low. assuming genlock is low, the device will then attempt to genlock the selected output clock and timing signals to the new input reference. if the output can be automatically genlocked to the new input reference, lock_lost will go low and the device will re-enter genlock mode. otherwise, the lock_lost pin will remain high and the device will enter free run mode. if vid_std[5:0] = 63 when the new reference is applied, the device will send the detected timing parameters to the clock synthesis and timing generator blocks. the new output format will start being generated du ring the first reference v period after the reference format has been reliably establ ished. the lock_lost pin will go low and the device will re-enter genlock mode. 3.5.4 allowable frequency drift on the reference by default, the frequency of the reference h pulse on hsync may drift from its expected value by approximately +/- 0.2% before the internal video pll loses lock. this tolerance may be adjusted using the max_ref_delta register at address 1eh of the host interface. the encoding scheme is shown in table 3-3 . the default value of the register is bh. note: regardless of the setting of this register, the device will always differentiate between 59.94hz and 60h z reference standards. table 3-3: max_ref_delta encoding scheme register setting maximum allowable frequency drift register setting maximum allowable frequency drift 0h +/- 2 -20 8h +/- 2 -12 1h +/- 2 -19 9h +/- 2 -11 2h +/- 2 -18 ah +/- 2 -10 3h +/- 2 -17 bh +/- 2 -9 4h +/- 2 -1 6 c h +/- 2 -8 5h +/- 2 -15 dh +/- 2 -7 6 h +/- 2 -14 eh +/- 2 - 6 7h +/- 2 -13 fh +/- 2 -5 the maximum allowa b le frequen c y d rift is measure d as a fra c tion of the frequen c y of the referen c e h pulse. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 50 of 119 3.6 genlock when both the ref_lost output and the genlock input are low, the device will attempt to genlock the output clock and timing signals to the input reference. note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. the device will first attempt to automatically genlock the output to the input reference. this automatic locking process is described in section 3.6.1 on page 50 . if the output format selected is such that it is not commonly genlocked to the input reference, the gs4911b/gs4910b will not automa tically lock. in this ca se, the user may program designated registers to manually allow locking to occur. the manual locking process is described in section 3.6.2 on page 54 . the user may disable one or more of the recognized input standards from being used to genlock the output by setting the reference_standard_disable register located at address 11h - 14h of the host interface. if a reference is applied that is disabled in the reference_standard_disable register, both the automatic and manual locking process will fail when the application layer sets genlock = low. note: if the device is already genlocked to an input reference and the applied standard is subsequently disabled in the reference_standard_disable register, the device will remain locked. 3.6.1 automatic locking process the behaviour of the device when attempting to automatically genlock will depend on the status and format of the input reference with respect to the selected output format. vid_std[5:0] = 1 to 51: once reference validity is established and th e reference format is recognized, the device uses an internal cross-reference genlock look-up table to determine whether the input can be used to genlock the output. a simplified version of this look-up table is shown in table 3-4 . the table represents a matrix with the vid_std[5:0] number representation of each possible reference format along the top axis, and the vid_std[5:0] representation of each possible output timing format along the vertical axis. a shaded box indicates that the output format can be automatically genlocked to the input reference. if the device determines that the output can be automatically genlocked to the input reference, it will lock the output format to the reference, adjust the output timing signals based on the genlock timing offset registers ( section 3.2.1.1 on page 38 ), and then set the lock_lost pin low. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 51 of 119 if the device cannot automatically genlock the output to the applied reference, the lock_lost pin will be set high and the device will operate in free run mode. in this case, the user may program designated registers to manually allow locking to occur ( section 3.6.2 on page 54 ). individual h, v, and f-locked signals can be read from the genlock_status register of the host interface. additionally, designated bits in the genlock_control register may be configured to permit the genlock block to ignore invalid timing on the hsync, vsync, or fsync pin when determining the locked status of the device. these registers are described in section 3.12.3 on page 79 . note: when attempting to lock some output graphics standards to an input reference, the device will automatically modify the output frame rate from the vesa standard to permit cross-locking to occur. the exact change will depend on the output standard selected and the input reference detected. standards affected by this behaviour are denoted by an 'a' or a 'b' suffix in table 3-4 . vid_std[5:0] = 62: setting vid_std[5:0]=62 allows custom timing signals to be programmed in the host register (see section 3.10 on page 74 ). it has the additional feature of disabling the validity check of the input reference signal. the device will automatically attempt to genlock the custom output to the input using the same process that is used when vid_std[5:0] = 1 to 51. the user must manually program the internal genlock block if a custom h-based timing output signal is programmed or if a custom reference pulse is applied to hsync. vid_std[5:0] = 63: when vid_std[5:0]=63, the device will send the detected input reference timing parameters to the clock synthesis and timing generator blocks. the device will produce an output format with identical timing to the input reference. it will then lock the output format to the reference, adjust the output timing parameters based on the genlock timing offset registers ( section 3.2.1.1 on page 38 ), and set the lock_lost pin low. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 52 of 119 table 3-4: cross-reference genlock table input referen c e format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 25 2 6 27 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 48 49 50 51 52 53 54 1 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 25 2 6 27 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 53 of 119 47 48 49 50 51 c ontinue d on next pa g e... 39a 42a 45a 4 6 a 49a 50a 39 b 40 b 42 b 43 b 45 b 4 6b 49 b 50 b 51 b note s : s uffix a num b ers are mo d ifie d from the ve s a stan d ar d to have exa c t 6 0hz, 75hz, or 85hz frame rates. s uffix b num b ers are mo d ifie d from the ve s a stan d ar d to have 6 0/1.001hz, 75/1.001hz, or 85/1.001hz frame rates. a sha d e d b ox in d i c ates that the sele c te d output format c an b e automati c ally g enlo c ke d to the input referen c e. table 3-4: cross-reference genlock table (continued) input referen c e format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 25 2 6 27 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 48 49 50 51 52 53 54 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 54 of 119 3.6.2 manual locking process using the host interface, the gs4911b/gs 4910b may be manually programmed to genlock certain video formats and audio clocks that are not automatically genlocked by the device. the following sections discuss when the user should manually program the internal video and/or audio genlock block, and how these blocks are programmed. 3.6.2.1 programming the internal video genlock block and output line/frame reset registers the user will be required to manually program the internal video genlock block and output line/frame reset registers during any of the following situations: 1. the pre-programmed output format and input reference cannot be automatically genlocked according to the cross-reference genlock table ( table 3-4 in section 3.6.1 on page 50 ). 2. a custom video clock is programmed in the host interface ( section 3.9.1 on page 72 ). 3. vid_std[5:0] = 62 and a custom h-based timing output signal is programmed (see section 3.10 on page 74 ). 4. vid_std[5:0] = 62 and a custom refere nce pulse is applied to hsync (see section 3.10.1 on page 75 ). video genlock block host registers a simplified vers ion of the gs4911b/gs4910b?s intern al video genlock block is shown in figure 3-6 . fi g ure 3- 6 : internal vi d eo g enlo c k blo c k to genlock the output clock and video timing signals to the input format, the user must first lock the frequency of the output video clock (f out ) to the frequency of the reference pulse on hsync (f href ). this is accomplished by programming the set of integers (h_feedback_divide, h_reference_divide) in the equation: where: f out = output video clock frequency f href = reference h pulse frequency on hsync h_feedback_divide = numerator of the divide ratio (host register 28h-29h) h_reference_divide = denominator of the divide ratio (host register 2ah-2bh) internal video genlock block h_feedback_divide h_reference_divide phase comparator clock synthesizer 27mhz hsync output video clock f href ( ( (host address 2ah - 2bh) (host address 28h - 29h) f out ( ( gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 55 of 119 before programming h_feedback_divide and h_reference_divide, the numerator and denominator must be reduced to their lowest factors. for example, to manually genlock an output format with a 74.25mhz video clock to a reference with a 27mhz video clock and 1716 cl ocks per line, the fo llowing calculations are necessary: therefore, program h_feedback_divide = 4719 and h_reference_divide = 1. output line/frame reset host registers in addition to programming h_feedback_divide and h_reference_divide, the user must also define the ratio of the output frame rate to the reference frame rate. the denominator of this ratio is programmed in the output_fv_reset register at address 18h of the host interface. before output_fv_reset is programmed, the numerator and denominator must be reduced to their lowest factors. two examples are demonstrated below: example 1: the reference has a frame rate of 30hz and the output frame rate is 50hz: therefore, program output_fv_reset = 3. the numerator does not have to be programmed. example 2: the reference has a frame rate of 29.97hz and the output frame rate is 50hz: therefore, program output_fv_reset = 600. the numerator does not have to be programmed. additionally, the frame_divider_reset register (address19h) must be configured to initialize the counter reset programmed in register 18h. h_feedback_divide h_reference_divide ------------------------------------------------- - f out f href ------------ - = f href 27 1716 ----------- - mhz = h_feedback_divide h_reference_divide ------------------------------------------------- - 74.25 mhz 27 1716 ----------- - mhz --------------------------- 7 4 . 2 5 1716 27 ----------- - 127413 27 ----------------- - 4719 1 ----------- - = == = output frame rate input frame rate ---------------------------------------------- 50 30 ----- - 5 3 -- - = = output frame rate input frame rate ---------------------------------------------- 50 29.97 ------------- 1001 600 ----------- - = = gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 56 of 119 alternatively, depending on the informat ion available, the user may program the output_h_reset register (address 17h) inst ead of programming registers 18h and 19h. output_h_reset defines the denominator of the ratio of the output line frequency to the input line frequency. before output_h_reset is programmed, the numerator and denominator must be reduced to their lowest factors. for example, to genlock the output standard 720p/59.94 at 74.25/1.001mhz to the input standard 525i/29.97 at 27mhz: therefore, program output_h_reset = 7. the numerator does not have to be programmed. note: either register 17h or registers 18h and 19h should be programmed. programming all three registers will trigger two counter resets. programming output_fv_reset is preferred in all cases except where a custom reference pulse is used in vid_std[5:0] = 62 (see section 3.10.1 on page 75 ). in this case, output_h_reset must be used. 3.6.2.2 programming the internal audio genlock block (gs4911b only) by default, the audio clocks are always genloc ked to the output video clock. however, if a custom video or audio clock is programmed in the host interface (see section 3.9 on page 72 ), the user must manually progra m the internal audio genlock block. a simplified vers ion of the gs4911b?s internal au dio genlock block is shown in figure 3-7 . fi g ure 3-7: internal au d io g enlo c k blo c k to genlock the audio clock to the video cl ock, the user must lock the fundamental sampling frequency (f s ) to the frequency of the output video clock (f out ). this is input line frequency input video clock frequency video clocks per input h ---------------------------------------------------------------------- 27000000 1716 ----------------------- - == ouput line frequency output video clock frequency video clocks per output h -------------------------------------------------------------------------------- 74250000 1650 ----------------------- - 1000 1001 ----------- - == output line frequency input line frequency ------------------------------------------------------- - 74250000 1000 1716 27000000 1001 1650 ------------------------------------------------------------ 20 7 ----- - == internal audio genlock block a_feedback_divide a_reference_divide phase comparator clock synthesizer 27mhz integer multiple of the fundamental audio sampling clock (host address 3dh - 3eh) (host address 3bh - 3ch) f s (n ( output video clock f out ( ( * gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 57 of 119 accomplished by programming the set of integers (a_feedback_divide, a_reference_divide) in the equation: where: f s = the fundamental audio sampling frequency f out = output video clock frequency a_feedback_divide = numerator of the divide ratio (host register 3bh-3ch) a_reference_divide = denominator of the divide ratio (host register 3dh-3eh) n = an integer constant the integer constant, n, will depend on the fundamental audio sampling frequency. it will be one of the three values as defined in table 3-5 . before programming a_feedback_divide and a_reference_divide, the numerator and denominator must be reduced to their lowest factors. for example, to manually genlock a custom audio clock with a fundamental sampling frequency of 42khz to a 27mhz video clock, the following calculations are necessary: therefore, program a_feedba ck_divide = 1792 and a_refere nce_divide = 1125. note that n=1024 when programming a custom audio clock (see section 3.9.2 on page 73 ). table 3-5: integer constant value asr_sel[2:0]=100b enable_384fs = 0 value of constant (n) no x 3072 ye s ye s 1024 ye s no 153 6 note s : 1. enable_384fs corresponds to bit 5 of address 31h of the host interface. it is low by default. 2. x signifies dont care. this bit will be ignored when determining n. a _feedback_divide a _reference_divide -------------------------------------------------- n f s f out ---------- = n = 1024 a _feedback_divide a _reference_divide -------------------------------------------------- 1024 42000 27000000 ----------------------- - 43008 27000 -------------- - 1792 1125 ----------- - = = = gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 58 of 119 3.6.3 adjustable locking time the gs4911b/gs4910b offers two different locking mechanisms to a llow the user to control the pll lock time and the integrity of the output signal during the locking process. the locking process is said to take place after the application of the input reference and before the lock_lost signal is set low. by default, the internal pll will crash lock. this locking process will ensure a minimum pll locking time; however, crash lock will cause the phase of the output clock and timing signals to jump during the locking process. the crash behaviour of the video pll is controlled by the crash_time bits of register address 24h. alternatively, the user may set bit 1 of register 16h high to force the pll to drift lock. drift lock will increase the lock ing time of the pll, but will maintain the signal integrity of the output clock and timing pulses during the locking process. as discussed in section 3.5.3 on page 47 , the device will norma lly drift lock when the reference is removed and subsequently re-applied during genlock mode. 3.6.4 adjustable loop bandwidth the default loop bandwidth of the gs4911b/gs 4910b's internal vide o pll is 10hz when the output video standard is the same as the input reference format. for other cross-locking combinations, the default loop bandwidth may be smaller than 1hz or as large as 30hz. the user may adjust the loop bandwidth of both the video and audio plls to a value that depends on the input, output, and audio standards selected, as well as on the amplitude of the jitter present on the applied hsync signal. increasing the loop bandwidth will result in a shorter pll lock time, but will a llow more freque ncy components of jitter to be passed to the outputs. decreasing the loop bandwidth will decrease the output jitter, but will result in a longer pll lock time. 3.6.4.1 loop bandwidth of the video pll the capacitive component of the filter controlling the video loop bandwidth is determined by the video_cap_genlock register and the resistive component is determined by the video_res_genlock register. these two registers are located at addresses 26h and 27h, respectively, of the host interface. to determine the setting of video_res_genlock and video_cap_genlock, the following equations must be solved: video_res_genlock 47 log 2 6 bw jitterin h_feedback_divide () + = video_cap_genlock video_res_genlock 21 ? gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 59 of 119 where: bw = the desired video pll loop bandwidth jitterin = jitter present on applied hsync reference signal, in seconds h_feedback_divide = the numerator of the video pll divide ratio h_feedback_divide represents the numerator of the ratio of the output clock frequency to the frequency of the h reference pulse. it is calculated as described in section 3.6.2.1 on page 54 . note: the bandwidth calculation represented by the above equation is only approximate. as the programmed value of video_res_genlock becomes larger, the approximation becomes more accurate. for example, the following steps are necess ary to program a loop bandwidth of 25hz given the following conditions: input hsync jitter = 3 ns, vid_std[5:0] = 3 and input reference format = ntsc. 1. calculate h_feedback_divide (as defined in section 3.6.2.1 on page 54 ): therefore, h_feedback_divide = 1716. 2. calculate the value for video_res_genlock: 3. calculate the value for video_cap_genlock: therefore, program video_res_genloc k = 37 and video_cap_genlock = 16. note: the value programmed in the video_res_genlock register must be between 32 and 42. the value programmed in the video_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. h_feedback_divide h_reference_divide ------------------------------------------------- - f pclkout f hrefin -------------------- - f pclkout 27 mhz = f hrefin 27 1716 ----------- - mhz = h_feedback_divide h_reference_divide ------------------------------------------------- - 27 1716 27 ----------- - 1716 1 ----------- - = = video_res_genlock 47 log 2 625 310 9 ? () 1716 () + 37 == video_cap_genlock 37 21 ? 16 == gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 60 of 119 3.6.4.2 loop bandwidth of the audio pll (gs4911b only) the capacitive component of the filter controlling the audio loop bandwidth is determined by the audio_cap_genlock register and the resistive component is determined by the audio_res_genlock register. these two registers are located at addresses 39h and 3ah, respectively, of the host interface. to determine the setting of audio_res_genlock and audio_cap_genlock, the following equations must be solved: where: bw = the desired audio pll loop bandwidth jitterin = jitter present on output pclk, in seconds. a_feedback_divide = the numerator of the audio pll divide ratio a_feedback_divide is calculated in the same way as demonstrated in section 3.6.2.2 on page 56. note: the bandwidth calculation represented by the above equation is only approximate. as the programmed value of audio_res_genlock becomes larger, the approximation becomes more accurate. note2: the value programmed in the audio_ res_genlock register must be between 32 and 42. the value programmed in the audio_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. 3.6.5 locking to digital ti ming from a deserializer as described in section 3.4.1 on page 43 , the gs4911b/gs4910b ma y be genlocked to either an analog reference, such as a blac k & burst signal, or to an sdi input via the digital h, v, and f blanking signals normally produced by a deserializer. when locking to an sdi input, the user should consider the possibility of a switch of the sdi signal upstream from the system. if the gs4911b/gs4910b is locked to the digi tal h, v, and f blanki ng signals produced by a deserializer, and the sdi input to the dese rializer is switched such that the phase of the h input changes abruptly, the ref_lost output will remain low and the gs4911b/gs4910b will not crash lock to the new h phase. instead, the clock and timing outputs will very slowly drift towards the new phase. during this period of drift, the lock_lost output will be low, even though the device is not genlocked. the user should clear the run_window bits [2:0] of register address 24h to force the device to crash lock should such a switch occur. this will cause the gs4911b/gs4910b to crash lock whenever it sees a disturbance of the input h signal. audio _res_genlock 47 log 2 6 bw jitterin a _feedback_divide () + = audi o_cap_genlock audio_res_genlock 21 ? gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 61 of 119 note: any action that causes an abrupt phase change of the h input to the gs4911b/gs4910b such that ref_lost is not tr iggered will cause the device to respond in the manner described above. in addition to the slow drifting behaviour outlined above, there may also be a random phase difference between the input vsync and output v sync signals occurring each time a switch in the sdi stream causes an abrupt phase change of the h input to the gs4911b/gs4910b. this will only occur when attemp ting to lock the ? f/1.001 ? hd output standards to th e 525-line sd input refe rences standards, or vice versa. for cases where the user must manually video genlock the device, the problem will occur whenever the value programmed for h_reference_divide (registers 2b-2ah) is greater than 1. all line-based timing outputs are affected. the only way to ensure a constant phase difference between the input vsync signal and the line-based timing outputs is to reset the line-based counters after such a switch occurs. this is achieved by to ggling bit 15 of register addre ss 83h in the host interface. the device will then delay all line-based output timing signals by vsync lines relative to the input vsync reference, as described in note 3 of section 3.2.1.1 on page 38 . 3.7 clock synthesis the clock synthesis circuit generates th e video/graphics clocks based on the vid_std[5:0] pins and host register settings . in the gs4911b, the clock synthesis circuit also generates the audio clock signals based on the asr_sel[2:0] pins and host register settings. the generated video and audio clocks may be further divided and are presented to the application layer via pins pclk1-pc lk3 and aclk1-aclk 3 respectively. 3.7.1 video clock synthesis the programmable video clock generator is re ferenced to an internal crystal oscillator and is responsible for generating the pclk output signals. the crystal oscillator requires an external 27mhz crystal connected to pins x1 and x2, or can be driven at lvttl levels from an external 27mhz source connected to x1. these two configurations are shown in figure 1-1 . a range of 8 different video sample clock ra tes and 13 different graphic display clock rates may be selected using the vid_std[5:0] pins of the device. section 1.4 on page 20 lists the video and graphic formats available using the vid_std[5:0] pins. once the device is powered up and an initial output format is selected us ing vid_std[5:0], the video clock rate may also be modified via the host interface (see section 3.9 on page 72 ). if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video stan dard may inst ead be selected via the vid_std[5:0] register of the host interface (see section 3.12.3 on page 79 ). although the external vid_std[5:0] pins wi ll be ignored, they should not be left floating. note: if vid_std[5:0] is set to 62 on power-up, the video clock will run at a frequency based on the internal default settings of the chip until the user programs registers 20h to gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 62 of 119 23h. please see section 3.9 on page 72 for a detailed explanation of custom clock generation. once the video clock has been generated, it will be presented to the application layer via the pclk1 to pclk3 pins. by default, each of the 3 video clock outputs will produce the generated fundamental clock frequency. however, it is possible to select other rates for each pclk output by programming the pclk_phase/divide registers beginning at address 2ch of the host interface (see section 3.12.3 on page 79 ). each pclk output may be individually programmed to provide one of the following: ? pclk fundamental frequency ? fundamental frequency /2 ? fundamental frequency /4 when all six vid_std[5:0] pins are set low, the video clocks will be disabled. pclk1 and pclk2 will go low and pclk3/pclk3 will be high impedance. note: if the pclk divider bits of registers 2ch - 2eh are set to enable a divide by 2 or divide by 4, the resultant divided clock will align with the falling edge of the output h sync timing signal either on its rising or falling edge. the pclk1 to pclk3 outputs may also be individually delayed with respect to the eight timing_out signals to allow for sk ew control downstream from the gs4911b/gs4910b. using the pclk _phase/divide regi sters, the phase of each clock may be delayed up to a no minal 10.3ns in 16 steps of approximately 700ps each ( table 3-6 ). this delay is available in addition to the genlock timing offset phase adjustment described in section 3.2.1 on page 38 . additionally, the current drive capability of pclk1 and pclk2 may be set high or low using the pclk_phase/divide registers. by default the current drive will be low. it must be set high if the clock rate is greater than 100mhz. table 3-6: video clock phase adjustment host settings p c lkn_phase[3:0] s ettin g 0 h 1h 2h 3h 4h 5h 6 h7h8h9hahbh c hdheh fh phase in c rement (ns) 0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5. 66 .3 7.0 7.7 8.4 9.1 9.8 10.3 note s : 1. the phase increments listed above are nominal values. 2. the phase of pclk is delayed re lative to the timing_out pins. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 63 of 119 3.7.2 audio clock synthesis (gs4911b only) the programmable audio clock generator is referenced to the internal pclk signal and is responsible for generating the aclk outp ut signals. three audio clock output pins, aclk1 to aclk3, are available to the application layer. the fundamental sampling frequency, fs, is selected using the asr_sel[2:0] pins as shown in table 3-7 . once selected, the audio clock rate may be customized via the host interface (see section 3.9 on page 72 ). if desired, the external asr_sel[2:0] pins may be ignored by setting bit 2 of the audio_control register and the sampling frequency may instead be programmed in the asr_sel[2:0] regi ster of the host interface (see section 3.12.3 on page 79 ). although the external asr_sel[2:0] pins will be ignored, they should not be left floating. when all three asr_sel[2:0] pins are set low, the audio clock outputs will be high impedance. in this case, the application layer may continue to power the aud_pll_vdd pin; however, to minimize noise and power consumption, aud_pll_vdd may be grounded. by default, after system reset, aclk1 to ac lk3 will output clock signals at 256fs, 64fs, and fs respectively. different division ratios for each output pin may be selected by programming the aclk_fs_multiple register s beginning at address 3fh of the host interface (see section 3.12.3 on page 79 ). the encoding of this register is shown in table 3-8 . clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs, 64fs, fs, and z bit are selectable on a pin by pin basis. the z bit will go high for one fs period every 192 fs periods. its phase is not defi ned by any timing event in th e gs4911b, and so is arbitrary. table 3-7: audio sample rate select asr_sel[2:0] sampling frequency (khz) 000 au d io c lo c k g eneration disa b le d 001 32 010 44.1 011 48 100 9 6 101 s low 32* 110 s low 44.1* 111 s low 48* * s low 32, 44.1, an d 48 are availa b le only when the vi d eo stan d ar d sele c te d is 23.98, 29.97, or 59.94 frame rate b ase d . they refer to 32khz, 44.1khz, or 48khz multiplie d b y 1000/1001 to maintain the 1, 2, or 3 frame sequen c e normally asso c iate d with 24, 30, an d 6 0 fps vi d eo. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 64 of 119 the fs signal on aclk1-3 has an accurate 50% duty cycle, and can be used for left/right definition, with the following exception: if fs = 96khz and the user configures the host interface such that one of the three aclk pins is set to output a clock signal at 192fs or 384fs, the 512fs clock will have a 33% duty cycle. all audio clocks are initially reset on the rising edge of the afs pulse, ensuring that video to audio clock synchronization is correct. du ring normal operation, the audio clock edge is allowed to drift slightly with respect to th e afs pulse. by default, the audio clock will be reset directly by the afs pulse if it drifts more than approximately +/-0.1us from the rising edge of the afs pulse. however, after device reset, or after the application of a new input reference, the aclk outputs may sometimes be offset from the afs pulse by up to several microseconds. the offset will remain until the device is reset or the reference removed and re-applied. the user may avoid this offset by minimizing the width of the afs_reset_window using bits 9- 7 of register 31h for the duration of the audio pll locking process. once the audio pll is locked, bit 1 of register 1fh will be set high, and the afs_reset_window may be set as desired. see table 3-9 . note: to maintain correct audio clock fr equencies for some ve sa standards, the window tolerance shown in table 3-9 may have to be increased from its default setting. in this case, set the afs_reset_window register to 1xx. table 3-8: audio clock divider aclkn_fs_multiple[3:0] audio clock frequency 000 fs 001 6 4fs 010 128fs 011 192fs* 100 25 6 fs 101 384fs* 110 512fs** 111 z- b it *this settin g is only availa b le when the ena b le_384fs b it of the au d io_ c ontrol re g ister is hi g h. **512fs c lo c k will have a 33% d uty c y c le when the ena b le_384fs b it is hi g h an d fs = 9 6 khz. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 65 of 119 3.7.2.1 audio to video clock phasing the important aspect of the audio to video phase relates to the way in which the afs pulse is used to reset the audio clock dividers so as to line up the leading edge of the audio clocks with the leading edge of the h sync pulse on line 1 of the first field in the audio frame sequence. the afs pu lse is further discussed in section 3.8.2 on page 68 . 625i 50 format for the 48khz sampling rate, the audio to video phase relationship for 625/50i reference signals is provided by the device in acco rdance with the ebu recommended practice r83-1996. the start of an audio frame (fs cl ock) will align with the 50% point of the h sync input of line 1 of each video frame (+/- the allowable drift specified in table 3-9 ). 525i 59.94 format for 525/59.94 ntsc reference signals, the device will ob serve the 5-frame phase-relationship inherent with this video standard, aligning the audio clocks with the 50% point of the h sync input of line 1 on every fifth frame (+/- the allowable drift specified in table 3-9 ). the number of audio sample clocks during a video frame is shown in table 3-10 for 32, 44.1, and 48khz audio sampling frequencies. table 3-9: encoding scheme for afs_reset_window window tolerance (us) af s _reset_win d ow (a dd ress 31h) fs = 32khz fs = 44.1khz fs = 48 khz fs = 9 6 khz (ena b le_384fs = 1) fs = 9 6 khz (ena b le_384fs = 0) 000 0.044 0.033 0.030 0.030 0.044 001 0.084 0.0 6 2 0.057 0.057 0.084 010 ( d efault) 0.1 66 0.121 0.112 0.112 0.1 66 011 0.329 0.239 0.220 0.220 0.329 1xx 0. 6 54 0.475 0.437 0.437 0. 6 54 note: ?x? si g nifies ? d on?t c are.? the b it settin g will b e i g nore d . gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 66 of 119 the external 10fid input pin may be used to resynchronize other audio clock frequencies, according to table 3-10 , by applying an active signal during the reference hsync of line 1 of the appropriate video frame. please see section 3.4.2 on page 44 for more details on the 10fid input pin. in the case where 10fid is not presen t as a reference signal, the gs4911b will automatically generate an afs pulse appropriate to the format selected, and use it to create an audio frame sequence. host interface control of afs and 10fid alternatively, the user may program the device via the host interface to re-time the audio frame sequence and 10 field-id. using re gister 1ah, a pulse may be generated to reset the afs and/or 10fid dividers at th e start of an output video frame (see section 3.12.3 on page 79 ). if using the host interface to reset the afs pulse, the device may be configured to ignore the input 10fid reference pin. to disable th e signal on the external 10fid pin from resetting the afs output pulse, set bit 0 of the audio_control register high. if using the host interface to reset the 10fid pulse, the external 10fid pin must be grounded. table 3-10: audio sampling frequency to video frame rate synchronization audio samples per video frame au d io s ample rate (khz) 24fps 25fps 29.97fps 30fps 50fps 59.94fps 6 0fps 32 4000/3 1280 1 6 01 6 /15 3200/3 6 40 8008/15 1 6 00/3 44.1 3 6 75/2 17 6 4 147147/100 1470 882 147147/200 735 48 2000 1920 8008/5 1 6 00 9 6 0 4004/5 800 * fps = frames per se c on d . gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 67 of 119 3.8 video timing generator the internal pclk signal generated by the clock synthesis circuit is used to produce horizontal, vertical, and frame based timing output signals. the signals generated and available to the application layer via the timing_out pins are: h sync, h blanking, v sy nc, v blanking, f sync, f digi tal, de, 10fid, afs (gs4911b only), and user_1~4. these signals are defined in section 1.5 on page 26 . additional information pertaining to the 10fid, afs, and user_1~4 signals can be found in the sub-sections below. when the gs4911b/gs4910b is operating in ge nlock mode, the h, v, and f based output timing signals are synchronized to the h, v, and f reference signals applied to the inputs by the application layer. the video timing outputs may be offset from the input reference by programming the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 38 ). all timing_out signals have se lectable polarity. the default polarities for each signal are given in the descriptions in section 1.5 on page 26 . 3.8.1 10 field id pulse as described in table 1-3 , the 10 field id (10fid) outp ut signal is used in the identification of film to video cadence. it is only generated for 29. 97, 30, 59.94, and 60fps formats. the 10fid pulse is generated on every 5 th frame for 29.97 and 30fps formats, and every 10 th frame on 59.94 and 60fps formats. by default, the 10fid signal is set high on the leading edge of the h sync output for the duration of line 1 of field 1 at the start of the 10 field sequence. this is shown in figure 3-8 . alternatively, by setting bit 4 of the video_control register at address 4ch of the host interface, the 10fid output signal may be configured to go high (default polarity) on the leading edge of the h sync pulse of line 1 of the first field in the 10 field sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the 10 field sequence. this is shown in figure 3-9 . fi g ure 3-8: default 10fid output timin g 10fid output horizontal sync output total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 68 of 119 fi g ure 3-9: optional 10fid output timin g the phasing of the divide by n frame counter may be reset by an external pulse on the 10fid input pin, or via register 1ah of the host interface (see section 3.12.3 on page 79 ). note: if a 10fid input signal is not provided to the device, the 10fid output signal will be invalid until the user initiates a reset via the host interface. the user should also reset the 10fid signal via the host if at any time the h input reference signal is removed and then re-applied. 3.8.2 audio frame synchronizing pulse (gs4911b only) as described in table 1-3 , the audio frame synchronizing (afs) pulse identifies the frame, within an n frame sequ ence, in which the audio sample rate clock is aligned with the h sync of line 1. it is generated for all video formats. the leading edge of the afs output pulse is co-timed with the h sync corresponding to line 1 of every n th frame in the sequence, and therefore identifies the exact time at which the audio sample rate clock and video pclk have synchronous leading edges. the number of frames in the sequence, n, is determined by the video frame rate and the audio clock frequency. these are selected using the vid_std[5:0] and asr_sel[2:0] pins or via the host interface. by default, the afs pulse is 1 line long, as shown in figure 3-10 . alternatively, by setting bit 1 of the audio_control register, the afs output signal may be configured to go high on the leading edge of the h sync pulse of line 1 of the first field in the ?n? frame sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the sequence. the afs timing in this configuration is similar to the 10fid optional timing shown in figure 3-9 . 10fid output horizontal sync output total field line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 69 of 119 fi g ure 3-10: af s output timin g the phasing of the divide by n counter can be controlled by the 10fid input or via designated registers in the host interface. by default, the 10fid input pin controls the afs phase (in addition to controlling the 10fid phase); however, this feature may be disabled by se tting bit 0 of the audio_control register (see section 3.12.3 on page 79 ). in addition, the afs signal may be reset via register 1ah. 3.8.3 user_1~4 as described in table 1-3 , the gs4911b/gs4910b offers 4 user programmable output signals which are available independent of the selected output video format. each user signal is individually programmable and the polarity, position, and width of each output may be defined with respect to the digital output timing of the device. each output signal may be programmed in both the horizontal and vertical dimensions relative to the leading edges of h blanking and v blanking. if desired, the pulses produced may then be combined with a logical and, or, or xor function to produce a composite signal (for example, a horizontal back porch pulse during active lines only, or the active part of lines 15 through 20 for vertical information retrieval). by default, the and, or, and xor functions are disabled. therefore, when a user signal is selected using the output_select registers of the host interface, the signal will go low (default polarity) at the h_start pixel and return high after the h_stop pixel. setting the and bit high, for example, will cause the user signal to be active only when user_h is active and user_v is active (i.e. the pixel is between both h_start and h_stop and v_start and v_stop). see figure 3-11 . note: the effective horizontal range of the fo ur user-defined timing signals is [h_start + 1, h_stop], except when h_start = 1, in which case the range is [h_start, h_stop]. this prevents the user from specifying an output user signal that begins on pixel 2 of a line. in the case of interlaced output formats, the programmed vertical start and stop lines refer to the start and stop lines of the generated user signal on field 1. the start and stop lines of the user signal on the even fields will be v_start - 1 and v_stop - 1, respectively. afs_out horizontal sync output total line line 1 every n frames where: n = 1 @ 25fps: fs = 32khz n = 1 @ 25fps, 30fps & 60fps: fs = 44.1khz n = 1 @ 25fps, 30fps & 60fps; fs = 48khz n = 2 @ 24fps; fs = 44.1khz, 48khz n = 3 @ 24fps, 30fps & 60fps: fs = 32khz n = 5 @ 29.97fps & 59.94fps; fs = 48khz n = 15 @ 29.97fps & 59.94fps; fs = 32khz n = 100 @ 29.97fps; fs = 44.1khz n = 200 @ 59.94fps; fs = 44.1khz gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 70 of 119 for example, if vid_std[5:0] = 3, field 1 will have 263 lines and field 2 will have 262 lines. a user-defined vertical pulse programmed to start on line 12 and stop on line 17 will start on frame lines 12 and 274, and stop on fram e lines 17 and 279. the designated registers for programming ea ch user signal are located in the host interface beginning at address 57h. see section 3.12.3 on page 79 . fi g ure 3-11: u s er pro g ramma b le output s i g nal and=0, or=0, xor=0 (default) and=0, or=1 shading indicates when user_x signal is active h_start h_stop v_start v_stop and=1 h_start h_stop v_start v_stop h_start h_stop v_start v_stop and=0, or=0, xor=1 h_start h_stop v_start v_stop gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 71 of 119 3.8.4 timing_out pins the horizontal, vertical, and frame based timing output signals for the selected video format are available to the application la yer via the timing_out_1 to timing_out_8 pins. programmable crosspoint switch each timing_out pin outputs a default signal as shown in table 1-3 . alternatively, a crosspoint switch may be programmed via the eight output_select registers of the host interface, allowing the user to select which output signal is directed to each timing_out pin (see section 3.12.3 on page 79 ). any signal may be sent to more than one pin if desired. table 3-11 outlines the encoding scheme of the eight output_select registers, which begin at address 43h of the host interface. table 3-11: crosspoint select output_select_n bit settings output signal 0000 hi g h impe d an c e 0001 h s yn c 0010 h blankin g 0011 v s yn c 0100 v blankin g 0101 f s yn c 0110 f di g ital 0111 10fid 1000 de 1001 reserve d 1010 af s * 1011 u s er_1 1100 u s er_2 1101 u s er_3 1110 u s er_4 1111 reserve d *af s is only availa b le on the gs 4911b. the b it settin g 1010 b will b e i g nore d b y the gs 4910b. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 72 of 119 3.8.4.1 selectable current drive and polarity the current-drive of each timing output pin is also selectable via the output_select registers. the current drive of each timing_out pin is low by default. however, it may be set high to accommodate certain applications. additionally, the polarity register of the host interface may be programmed to select the polarity of each timing output signal. 3.9 custom cl ock generation in addition to the device?s pre-programmed clock frequencies, the user may generate a custom audio or video clock by programming designated registers in the host interface. custom video clock generati on is supported by both the gs4910b and gs4911b and is described in section 3.9.1 on page 72 . custom audio clock generation is only supported by the gs4911b and is described in section 3.9.2 on page 73 . 3.9.1 programming a custom video clock the fundamental frequency of the video cloc k is defined by the output video format initially set by vid_std[5:0]. at any time, this fundamental frequency may be modified to create a custom output video format. the user may generate a video clock with any frequency between 13.5mhz and 165mhz. by programming the pclk _divide registers, the output pclk may be as low as 13.5/4 = 3.375mhz. generating a custom video clock will change the period of the video timing signals presented to the timing_out pins; however, the pixels per line, lines per frame, and other pixel and line-based timing signals will remain unchanged. to redefine the pixel and line based timing parameters, registers 4eh to 55h must be reprogrammed as described in section 3.10 on page 74 . the frequency of the custom video clock is determined using a ratio based on the 27mhz reference. therefore, to program a custom clock, the user must calculate and program the set of integers (n v , d v ) in the equation: where: f out = desired output video clock frequency f in = 27mhz crystal reference n v = numerator of the ratio (host register 20h-21h) d v = denominator of the ratio (host register 22h-23h) n v d v ------ - f out f in ---------- = gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 73 of 119 before programming n v and d v , the numerator and denominator must be reduced to their lowest factors. two examples are given below: example 1: programming an output video clock of 74.25mhz: therefore, program n v = 11 and d v = 4. example 2: programming an output vi deo clock of 74.175824mhz (74.25/1.001): therefore, program n v = 250 and d v = 91. note: the nv and dv values programmed in registers 20h-21h and 22h-23h are not held until the custom video clock update bit (6) of register 16h is toggled. 3.9.2 programming a custom audio clock (gs4911b only) the gs4911b?s audio clocks are derived from the fund amental audio sampling frequency initially set by asr_sel[2:0]. at any time this fundamental sampling frequency may be modified to create a custom output audio clock. the user may generate any audio sampling frequency between 6.6khz and 96khz, and therefore create a custom audio clock as hi gh as 512*96khz. when generating a custom audio sampling frequency, asr_ sel[2:0] must be set to 100b and bit 5 of register 31h (enable_384fs) must be kept low. the fundamental sampling frequency is dete rmined using a ratio based on the 27mhz reference. therefore, to program a custom audio clock, the user must calculate and program the set of integers (n a , d a ) in the equation: where: f s = desired fundamental audio sampling frequency f in = 27mhz crystal reference n a = numerator of the ratio (host register 33h-34h) d a = denominator of the ratio (host register 35h-36h) before programming n a and d a , the numerator and denominator must be reduced to their lowest factors. f out f in ---------- 74.25 mhz 27 mhz --------------------------- = n v d v ------ - 7425 2700 ----------- - 11 4 ----- - == f out f in ---------- 74.25 1.001 ------------- mhz 27 mhz --------------------------- = n v d v ------ - 7425 1000 2700 1001 ----------------------------- - 250 91 -------- - == n a d a ------ -1024 f s f in ------ - = gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 74 of 119 for example, to program a fundamental audio sampling frequency of 42khz: therefore, program n a = 1792 and d a = 1125 and toggle the custom audio clock update bit (6) of register 31h. usin g registers 3fh to 41h, the cu stom audio sampling frequency generated may then be multiplied by a fa ctor of 64, 128, 256, or 512 before being presented to the aclk pins. note: the afs reset described in section 3.7.2 on page 63 will always remain active. 3.10 custom output timing signal generation in addition to the devices?s pre-programmed output timing signals, the user may also build their own custom timing signals. this is achieved by setting vid_std[5:0] = 62 and programming designated host registers. when programming custom output timing signal s, the user must define the pixel, line, and field/frame timing parameters using regi sters 4eh to 55h of the host interface (see figure 3-12 ). for all custom formats, the vsync outp ut will start on line 1 of the video field. the user may delay the vsync pulse to any line using the v_offset register (see section 3.2.1.1). when the user sets vid_std[5:0] = 62, re gisters 4eh to 55h will become read/write configurable and the device will initially continue to output timing signals based on the video format previously selected. once the user has programmed all eight custom timing registers, generation of the new timing signals will begin. the frequency of the video clock will remain as previously select ed unless otherwise modified as described in section 3.9.1 on page 72 . note: if vid_std[5:0] = 62 on power-up, the initial output timing signals will be set to the internal default timing of the chip until the user programs 4eh to 55h. fi g ure 3-12: c ustom timin g parameters n a d a ------ - 1024 42000 27000000 ----------------------- - 43008 27000 -------------- - 1792 1125 ----------- - === h blankin g h s yn c c lo c ks_per_line (4eh) c lo c ks_per_hsyn c (4fh) hsyn c _to_ s av (50h) hsyn c _to_eav (51h) lines_per_fiel d (52h) lines_per_vsyn c (53h) vsyn c _to_first_a c tive_line (54h) vsyn c _to_last_a c tive_line (55h) v blankin g v s yn c gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 75 of 119 3.10.1 custom input reference as explained in section 3.5.2 on page 46 , when vid_std[5:0] = 62, the device will only verify that a stable signal with a period of less than 2.4ms is present on the hsync input pin before attempting to genlock. therefore, in addition to programming custom output timing signals, the user may genlock the ou tput timing signals to a custom reference pulse applied to hsync. in this case the user is required to manually program the video genlock block (see section 3.6.2.1 on page 54 ). 3.11 extended audio mode for hd demux using the gennum audio core the gs4911b/gs4910b has been designed to interface with gennum's fpga audio core in order to provide a 24.576mhz cloc k (512 * 48khz) locked to the audio clock contained in the embedded audio data packets of an hd-sdi stream. it is the responsibility of the user to divide this clock by 4 to obta in the 6.144mhz required by the core. in hd demux mode, the fpga audio core will extract an audio clock from the embedded audio data packet s and present a 24khz clock to the gs4911b/gs4910b via the aclkdiv2a (for group a) and aclkdiv2b (for group b) outputs. the embedded clock must be 48khz. the 24khz reference signals for each audio group must be applied to the hsync input pin of a gs4911b/gs4910b, while a divided versio n of this signal must be applied to the vsync input pin. the divided signal must meet the requirements for vsync validity given in section 3.5.2 on page 46 . it is recommended that the vsync signal be generated by dividing the 24khz reference appl ied to hsync by 512 to give 46.875hz. to enable the extended audio mode, the user must do the following: 1. set vid_std[5:0] = 04h. 2. set the f_lock_mask and v_lock_mask bits [4:3] of register address 16h to 1. 3. set the ext_audio_mode regi ster address 81h to 20c1h. 4. toggle the update_custom_v_clock bit [6] of register address 16h. in this mode, the gs4911b/gs4910b will prod uce a 24.576mhz clock on its pclk output pins that is locked to the 24khz extracted audio clock reference applied to hsync. it will not lock to any other reference frequency. the user may then divide this frequency by 4 using the programmable di viders in the gs4911b/gs4910b. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 76 of 119 fi g ure 3-13: au d io c lo c k blo c k dia g ram for hd demux operation 3.12 gspi host interface the gspi, or gennum serial peripheral interfac e, is a 4-wire interface provided to allow the host to enable addition al features of the gs4911b /gs4910b and/or to provide additional status information through configuration registers in the device. the gspi comprises a serial data input signal , sdin, a serial data output signal, sdout, an active low chip select, cs , and a burst clock, sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin, jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pin is a non-clocked loop-through of sdin and may be connected to the sdin pin of another device, allowing multiple devices to be connected to the gspi chain. the interface is illustrated in figure 3-14 . fp g a aout1_2 aout3_4 aout5_ 6 aout7_8 s erial vi d eo input hd audio demux c ore p c lk gs 49xxb vi d eo data w c lka gs 1559 deserializer a c lk 6 4a w c lk b p c lk1 a c lk128 b a c lk 6 4 b vin[19:0] p c lk a c lk d iv2 b p c lk1 gs 49xxb a c lk128a a c lk d iv2a /512 /512 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 77 of 119 fi g ure 3-14: gs pi appli c ation interfa c e c onne c tion all read or write access to th e gs4911b/gs4910b is initiated and terminated by the host processor. each access always begins with a 16-bit comman d word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. 3.12.1 command word description the command word consists of 16 bits transmitted msb first and includes a read/write bit, an auto-increment bit and a 12-bit address. figure 3-15 shows the command word format and bit configurations. command words are clocked into the gs4911b/gs 4910b on the rising ed ge of the serial clock, sclk, which operates in a burst fashion. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operat ion. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses. this facilitates multiple address writes without sendin g a command word for each data word. auto-increment may be used for both read and write access. fi g ure 3-15: c omman d wor d format application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 gs4911b/gs4910b cs gs4911b/gs4910b msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 78 of 119 fi g ure 3-1 6 : data wor d format 3.12.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 3-17 and figure 3-18 respectively. the timing parameters are defined in table 3-12 . when several devices are connected to the gspi chain, only one cs should be asserted during a read sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin as is. where several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 table 3-12: gspi timing parameters parameter definition specification t 0 the minimum d uration of time c hip sele c t, cs , must b e low b efore the first sc lk risin g e dg e. 1.5 ns t 1 the minimum sc lk perio d . 100 ns t 2 duty c y c le tolerate d b y sc lk. 40% to 6 0% t 3 minimum input setup time. 1.5 ns t 4 the minimum d uration of time b etween the last sc lk c omman d wor d (or d ata wor d if the auto-in c rement b it is hi g h) an d the first sc lk of the d ata wor d (write c y c le). 37.1 ns t 5 the minimum d uration of time b etween the last sc lk c omman d wor d (or d ata wor d if the auto-in c rement b it is hi g h) an d the first sc lk of the d ata wor d (rea d c y c le). 148.4 ns t 6 minimum output hol d time (15pf loa d ). 1.5 ns t 7 the minimum d uration of time b etween the last sc lk of the gs pi transa c tion an d when cs c an b e set hi g h. 37.1 ns t 8 minimum input hol d time. 1.5 ns gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 79 of 119 fi g ure 3-17: gs pi rea d mo d e timin g fi g ure 3-18: gs pi write mo d e timin g 3.12.3 configuration and status registers table 3-13 summarizes the gs4911b/gs4910b's in ternal status an d configuration registers. all registers are available to the host via th e gspi and are all individually addressable. sclk cs sdin sdout t 5 t 6 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 3 sclk cs sdin sdout t 0 t 1 t 2 t 4 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 7 t 8 table 3-13: configuration and status registers register name address bit description r/w default r s vd 00h - 09h ? reserve d .?? h_perio d 0ah 15-0 c ontains the num b er of 27mhz pulses in the input h s yn c perio d . this re g ister is set b y the referen c e format dete c tor b lo c k usin g the h s yn c si g nal present on the external h s yn c input pin. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent h s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 80 of 119 h_1 6 _perio d 0bh 15-0 c ontains the num b er of 27mhz pulses in 1 6 h s yn c perio d s. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the h s yn c si g nal present on the external h s yn c input pin. it is useful for 1/1.001 d ata d ete c tion. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent h s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a v_lines 0 c h 15-0 c ontains the num b er of h s yn c perio d s in the input v s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a v_2_lines 0dh 15-0 c ontains the num b er of h s yn c perio d s in 2 v s yn c intervals. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a f_lines 0eh 15-0 c ontains the num b er of h s yn c perio d s in the input f s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d f s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e is applie d . if the new referen c e d oes not in c lu d e an f s yn c pulse, this re g ister will b e set to zero. referen c e: s e c tion 3.5.1 on pa g e 45 rn/a table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 81 of 119 h_1 6 _perio d 0bh 15-0 c ontains the num b er of 27mhz pulses in 1 6 h s yn c perio d s. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the h s yn c si g nal present on the external h s yn c input pin. it is useful for 1/1.001 d ata d ete c tion. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent h s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a v_lines 0 c h 15-0 c ontains the num b er of h s yn c perio d s in the input v s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a v_2_lines 0dh 15-0 c ontains the num b er of h s yn c perio d s in 2 v s yn c intervals. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 45 rn/a f_lines 0eh 15-0 c ontains the num b er of h s yn c perio d s in the input f s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d f s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e is applie d . if the new referen c e d oes not in c lu d e an f s yn c pulse, this re g ister will b e set to zero. referen c e: s e c tion 3.5.1 on pa g e 45 rn/a table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 82 of 119 input_ s tan d ar d 0fh 15-13 reserve d . s et these b its to zero when writin g to 0fh. ?? 0fh 12 for c e_input - s et this b it hi g h to for c e the gs 4911b/ gs 4910b to re c o g nize the applie d input referen c e format as the stan d ar d pro g ramme d in b its 11- 6 of this re g ister. referen c e: s e c tion 3.2.1.2 on pa g e 41 r/w 0 0fh 11- 6 for c e d _ s tan d ar d - when b it 12 is set hi g h, the gs 4911b/ gs 4910b will use the value pro g ramme d in these b its, rather than the value in b its 5-0, to d etermine the input referen c e format. the 6 - b it value pro g ramme d here shoul d always c orrespon d to the vid_ s td[5:0] value of the applie d referen c e. these b its shoul d only b e pro g ramme d as part of the freeze mo d e pro c e d ure d es c ri b e d in s e c tion 3.2.1.2 on pa g e 41 . r/w 0 0fh 5-0 dete c te d _ s tan d ar d - c ontains the vi d eo stan d ar d applie d to the input referen c e pins on c e it has b een d ete c te d . these b its are set b y the referen c e format dete c tor b lo c k an d c orrespon d to the vid_ s td[5:0] value of the stan d ar d as liste d in ta b le 1-2 . the dete c te d _ s tan d ar d b its will b e set to zero if no input referen c e si g nal is applie d or if the input referen c e si g nal is not an automati c ally re c o g nize d vi d eo format. otherwise the value will b e b etween 1 an d 54. referen c e: s e c tion 3.5.2 on pa g e 4 6 r/w n/a am b _ s t d _ s el 10h 15-11 reserve d . s et these b its to zero when writin g to 10h. ?? 10h 10-0 the user may set this re g ister to d istin g uish b etween d ifferent formats that look i d enti c al to the internal referen c e format dete c tor b lo c k. s ee ta b le 3-2 . referen c e: s e c tion 3.5.2.1 on pa g e 4 6 r/w 0 referen c e_ s tan d ar d _disa b le 14h-11h 6 3-0 the referen c e_ s tan d ar d _disa b le re g isters may b e use d to d isa b le one or more of the re c o g nize d input stan d ar d s from b ein g use d to g enlo c k the output. this is d one b y settin g the b it hi g h that c orrespon d s to the vid_ s td[5:0] value of the vi d eo stan d ar d in ta b le 1-2 . for example, if b it 5 is set hi g h, then the output c lo c k an d timin g si g nals will not g enlo c k to an input referen c e with timin g c orrespon d in g to vid_ s td[5:0] = 5 in ta b le 1-2 . a dd ress 11h = b its 15-0 a dd ress 12h = b its 31-1 6 a dd ress 13h = b its 47-32 a dd ress 14h = b its 6 3-48 referen c e: s e c tion 3. 6 on pa g e 50 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 83 of 119 g enlo c k_ s tatus 15h 15- 6 reserve d .?? 15h 5 referen c e_lo c k - this b it will b e hi g h when the output is su cc essfully g enlo c ke d to the input (i.e. when b its 4-1 of this re g ister are hi g h an d are not maske d b y b its 4-2 of re g ister 1 6 h). the lo c k_lo s t output pin is an inverte d c opy of this b it. referen c e: s e c tion 3. 6 .1 on pa g e 50 rn/a 15h 4 f_lo c k - this b it will b e hi g h when the output f is su cc essfully g enlo c ke d to the f s yn c input. note: if the input referen c e d oes not in c lu d e an f s yn c input, this b it will have the same settin g as v_lo c k ( b it 3). referen c e: s e c tion 3. 6 .1 on pa g e 50 rn/a 15h 3 v_lo c k - this b it will b e hi g h when the output v is su cc essfully g enlo c ke d to the v s yn c input. referen c e: s e c tion 3. 6 .1 on pa g e 50 rn/a 15h 2 h_lo c k - this b it will b e hi g h when the output h is su cc essfully g enlo c ke d to the h s yn c input. referen c e: s e c tion 3. 6 .1 on pa g e 50 rn/a 15h 1 c lo c k_lo c k - this b it will b e hi g h when the vi d eo c lo c k is lo c ke d to the internal v_pll and the au d io c lo c k is lo c ke d to the internal a_pll (i.e. b its 0 an d 1 of re g ister 1fh are hi g h). referen c e: s e c tion 3. 6 .1 on pa g e 50 rn/a 15h 0 referen c e_present - this b it will b e hi g h when a vali d input referen c e si g nal has b een applie d to the d evi c e. the ref_lo s t output pin is an inverte d c opy of this b it. referen c e: s e c tion 3.5.2 on pa g e 4 6 rn/a table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 84 of 119 g enlo c k_ c ontrol 1 6 h 15-7 reserve d . s et these b its to zero when writin g to 1 6 h. ?? 1 6 h 6 up d ate_ c ustom_v_ c lo c k - this b it is use d to up d ate the c ustom vi d eo c lo c k parameters pro g ramme d in re g isters 20h to 23h of the host interfa c e. all non-zero parameters in these re g isters will b e up d ate d via a low to hi g h transition on this b it. this b it is also use d to ena b le the exten d e d au d io mo d e of the d evi c e. r/w 0 1 6 h5 g enlo c k_from_host - set this b it hi g h to ena b le vi d eo g enlo c k c ontrol via the host interfa c e instea d of the external g enlo c k pin (see b it 0 of this re g ister). referen c e: s e c tion 3.2 on pa g e 37 r/w 0 1 6 h 4 f_lo c k_mask - if this b it is set hi g h, the gs 4911b/ gs 4910b will i g nore the status of f_lo c k ( b it 4 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 50 r/w 0 1 6 h 3 v_lo c k_mask - if this b it is set hi g h, the gs 4911b/ gs 4910b will i g nore the status of v_lo c k ( b it 3 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 50 r/w 0 1 6 h2h_lo c k_mask - if this b it is set hi g h, the gs 4911b/ gs 4910b will i g nore the status of h_lo c k ( b it 2 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 50 r/w 0 1 6 h1drift_ c rash - when this b it is set hi g h, the g enerate d vi d eo c lo c k will d rift lo c k to a new input referen c e rather than c rash lo c k. referen c e: s e c tion 3. 6 .3 on pa g e 58 r/w 0 1 6 h0 g enlo c k - this b it may b e use d instea d of the external pin to g enlo c k the output vi d eo format to the input referen c e. this b it will b e i g nore d if b it 5 of this re g ister is low. referen c e: s e c tion 3.2 on pa g e 37 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 85 of 119 output_h_reset 17h 15-0 when the output is g enlo c ke d to the input, the input referen c e is use d to reset the line- b ase d c ounter c ontrollin g the g enerate d timin g output si g nals. pro g rammin g this re g ister to a non-zero value will over-ri d e the internal pixel- b ase d c ounter. the c ounter reset will o cc ur every output_h_reset lines instea d of on a frame b asis. this re g ister is pro g ramme d when manually pro g rammin g the internal vi d eo g enlo c k b lo c k. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 54 r/w ? output_fv_reset 18h 15-0 when the output is g enlo c ke d to the input, the input referen c e is use d to reset the frame- b ase d c ounter c ontrollin g the g enerate d timin g output si g nals. pro g rammin g this re g ister to a non-zero value will over-ri d e the internal frame- b ase d c ounter. the c ounter reset will o cc ur every output_fv_reset input frames. this re g ister is pro g ramme d when manually pro g rammin g the internal vi d eo g enlo c k b lo c k. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g re g ister 19h. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 54 r/w ? frame_divi d er_reset 19h 15-2 reserve d . s et these b its to zero when writin g to 19h. ?? 19h 1 ref_f_ s yn c - when ref_f_mo d e ( b it 0 of 19h) is set hi g h, this b it is use d to initialize the frame- b ase d c ounter reset pro g ramme d in 18h. the reset pulse is g enerate d if this b it is pulse d (low to hi g h to low) d urin g the output frame imme d iately prior to the frame the reset is to o cc ur. this re g ister is pro g ramme d when manually pro g rammin g the internal vi d eo g enlo c k b lo c k. referen c e: s e c tion 3. 6 .2 on pa g e 54 r/w 0 19h 0 ref_f_mo d e - set this b it hi g h to initialize the frame- b ase d reset via the host interfa c e (usin g b it 1 a b ove). referen c e: s e c tion 3. 6 .2 on pa g e 54 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 86 of 119 10fid_af s _reset 1ah 15-4 reserve d . s et these b its to zero when writin g to 1ah. ?? 1ah 3 af s _reset ( gs 4911b only) - set this b it hi g h to use reset_ s yn c ( b it 0 of re g ister 1ah) to reset the output af s pulse. note: this b it will remain low in the gs 4910b. s et this b it low when writin g to a dd ress 1ah of the gs 4910b. referen c e: s e c tion 3.7.2.1 on pa g e 6 5 r/w 0 1ah 2 10fid_reset - set this b it hi g h to use reset_ s yn c ( b it 0 of re g ister 1ah) to reset the output 10fid pulse. note: if a 10fid input si g nal is not provi d e d to the d evi c e, the user must g enerate a reset usin g this b it to initiate the 10fid timin g output. in this c ase, the 10fid input pin must b e g roun d e d . referen c e: s e c tion 3.7.2.1 on pa g e 6 5 r/w 0 1ah 1 reserve d . s et this b it to zero when writin g to 1ah. ? ? 1ah 0 reset_ s yn c - resets the pulses d es c ri b e d in b its 2, an d 3 a b ove. the reset pulse is g enerate d if this b it is pulse d (low to hi g h to low) d urin g the output frame imme d iately prior to the frame the reset is to o cc ur. this reset will operate in d epen d ently of any other resets, for example from the referen c e input. r/w 0 h_offset 1bh 15-0 the output h si g nal may b e d elaye d with respe c t to the input referen c e b y the num b er of pixels pro g ramme d in this re g ister. ( s ee s e c tion 3.2.1.1 on pa g e 38 ). the value pro g ramme d in this re g ister shoul d not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . horizontal a d van c es may b e a c hieve d b y pro g rammin g a value equal to the maximum allowa b le offset minus the d esire d a d van c e. note: this re g ister is internally rea d b y the d evi c e on c e per fiel d . at that time any new value pro g ramme d is sent to the internal offset c ir c uitry. referen c e: s e c tion 3.2.1.1 on pa g e 38 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 87 of 119 v_offset 1 c h 15-0 the output v si g nal may b e d elaye d with respe c t to the input referen c e b y the num b er of lines pro g ramme d in this re g ister. ( s ee s e c tion 3.2.1.1 on pa g e 38 ). the value pro g ramme d in this re g ister shoul d not ex c ee d the maximum num b er of lines per frame of the out g oin g stan d ar d . verti c al a d van c es may b e a c hieve d b y pro g rammin g a value equal to the maximum allowa b le offset minus the d esire d a d van c e. note: this re g ister is internally rea d b y the d evi c e on c e per fiel d . at that time any new value pro g ramme d is sent to the internal offset c ir c uitry. referen c e: s e c tion 3.2.1.1 on pa g e 38 r/w 0 c lo c k_phase_offset 1dh 15-0 phase_offset - the output c lo c k an d d ata phase may b e offset with respe c t to the input referen c e b y the num b er of in c rements pro g ramme d in this re g ister. the in c rement step size d epen d s on the vi d eo c lo c k frequen c y. the en c o d in g s c heme for this re g ister is shown in ta b le 3-1 . note: this re g ister must b e c leare d to a c hieve a c lo c k phase offset of zero. referen c e: s e c tion 3.2.1.1 on pa g e 38 r/w 0 max_ref_delta 1eh 15-0 the value pro g ramme d in this re g ister c ontrols the allowe d d evian c e from the expe c te d frequen c y on the referen c e h s yn c b efore the internal vi d eo pll loses lo c k. the en c o d in g s c heme is shown in ta b le 3-3 . referen c e: s e c tion 3.5.4 on pa g e 49 r/w 000bh table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 88 of 119 vi d eo_ s tatus 1fh 15-5 reserve d .?? 1fh 4 ref_h_polarity - status re g ister to in d i c ate the d ete c te d h s yn c polarity ( ' 1 ' for positive, ' 0 ' for ne g ative). this b it will b e zero when no referen c e si g nal is present. referen c e: s e c tion 3.4.3 on pa g e 45 rn/a 1fh 3 ref_v_polarity - status re g ister to in d i c ate the d ete c te d v s yn c polarity ( ' 1 ' for positive, ' 0 ' for ne g ative). this b it will b e zero when no referen c e si g nal is present an d for d i g ital b lankin g input referen c es. referen c e: s e c tion 3.4.3 on pa g e 45 rn/a 1fh 2 ref_blank_timin g - status re g ister to in d i c ate the input d ete c tion of h b lankin g vs. h syn c timin g (?1? for b lankin g , ' 0 ' for syn c timin g ). this b it will b e zero when no referen c e si g nal is present. referen c e: s e c tion 3.4.3 on pa g e 45 rn/a 1fh 1 a_pll_lo c k ( gs 4911b only)- this b it will b e hi g h when the g enerate d au d io c lo c k is lo c ke d to the vi d eo c lo c k referen c e. note: this b it will remain hi g h in the gs 4910b. referen c e: b it 1 of re g ister 15h. rn/a 1fh 0 v_pll_lo c k - this b it will b e hi g h when the g enerate d vi d eo c lo c k is lo c ke d to the h s yn c input referen c e. referen c e: b it 1 of re g ister 15h. rn/a n v 21h-20h 31-0 a non-zero num b er pro g ramme d in this re g ister d efines the numerator fo r the ratio of the vi d eo c lo c k to the 27mhz referen c e. this re g ister c an b e use d for c reatin g c ustom vi d eo c lo c k frequen c ies. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 1 6 h. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 20h = b its 15-0 a dd ress 21h = b its 31-1 6 referen c e: s e c tion 3.9.1 on pa g e 72 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 89 of 119 d v 23h-22h 31-0 a non-zero num b er pro g ramme d in this re g ister d efines the d enominator for th e ratio of the vi d eo c lo c k to the 27mhz referen c e. this re g ister c an b e use d for c reatin g c ustom vi d eo c lo c k frequen c ies. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 1 6 h. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 22h = b its 15-0 a dd ress 23h = b its 31-1 6 referen c e: s e c tion 3.9.1 on pa g e 72 r/w ? c onst c f_ g enlo c k 24h 15-8 c rash_time - c ontrols the c rash lo c k perio d of vi d eo pll lo c kin g pro c ess. this time c ontri b utes to the total pll lo c k time g iven in the a c c hara c teristi c s ta b le. the time of the c rash pro c ess in h referen c e perio d s is d etermine d b y [ c rash_time x 4] + 1. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .3 on pa g e 58 r/w ? 24h 7-3 lo c k_lost_threshol d - c ontrols the threshol d of the lo c k in d i c ation c ir c uit. a lar g er value pro g ramme d in this re g ister c an in c rease the sta b ility of the lo c k_lo s t output si g nal when the input h referen c e si g nal is su b je c t to lar g e amounts of low frequen c y jitter. a lar g er value in this re g ister will also in c rease the lo c k in d i c ation time, althou g h not the a c tual lo c k time of the d evi c e. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . r/w ? 24h 2-0 run_win d ow - c ontrols the output frequen c y error in the c ase of a missin g or mis-time d h referen c e transition. the d efault value of this re g ister allows the d evi c e to maintain g enlo c k throu g h one missin g input h pulse. this feature c an b e d isa b le d b y pro g rammin g run_win d ow = 000 b . in this c ase, the d evi c e will imme d iately rea c t to any d istur b an c e of the input h si g nal. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3.5.3 on pa g e 47 r/w ? r s vd 25h ? reserve d .?? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 90 of 119 vi d eo_ c ap_ g enlo c k2 6 h 15- 6 reserve d . s et these b its to zero when writin g to 2 6 h. ?? 2 6 h5-0 c ontrol si g nal to a d just loop b an d wi d th of vi d eo g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 10 an d vi d eo_res_ g enlo c k - 21. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .4 on pa g e 58 r/w ? vi d eo_res_ g enlo c k 27h 15- 6 reserve d . s et these b its to zero when writin g to 27h. ?? 27h 5-0 c ontrol si g nal to a d just loop b an d wi d th of vi d eo g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 32 an d 42. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .4 on pa g e 58 r/w ? h_fee db a c k_divi d e 29h-28h 31-0 in the internal vi d eo g enlo c k b lo c k, this re g ister d efines the numerator of the d ivi d e ratio. this re g ister may b e pro g ramme d to manually g enlo c k the output to the input referen c e. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 28h = b its 15-0 a dd ress 29h = b its 31-1 6 referen c e: s e c tion 3. 6 .2.1 on pa g e 54 r/w ? h_referen c e_divi d e 2bh-2ah 31-0 in the internal vi d eo g enlo c k b lo c k, this re g ister d efines the d enominator of the d ivi d e ratio. this re g ister may b e pro g ramme d to manually g enlo c k the output to the input referen c e. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 2ah = b its 15-0 a dd ress 2bh = b its 31-1 6 referen c e: s e c tion 3. 6 .2.1 on pa g e 54 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 91 of 119 p c lk1_phase/divi d e2 c h 15-7 reserve d . s et these b its to zero when writin g to 2 c h. ?? 2 c h 6c urrent_p1 - sele c ts the c urrent d rive c apa b ility of the p c lk1 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. note: the c urrent d rive shoul d b e set hi g h if p c lk1 is g reater than 100mhz. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2 c h5-2p c lk1_phase - a d justs the output phase of the p c lk1 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2 c h1divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk1 b y four. note: s ettin g this b it an d b it 0 simultaneously hi g h will hol d the p c lk1 pin low. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2 c h0divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk1 b y two. note: s ettin g this b it an d b it 1 simultaneously hi g h will hol d the p c lk1 pin low. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 p c lk2_phase/divi d e 2dh 15-7 reserve d . s et these b its to zero when writin g to 2dh. ?? 2dh 6c urrent_p2 - sele c ts the c urrent d rive c apa b ility of the p c lk2 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. note: the c urrent d rive shoul d b e set hi g h if p c lk2 is g reater than 100mhz. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2dh 5-2 p c lk2_phase - a d justs the output phase of the p c lk2 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2dh 1 divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk2 b y four. note: s ettin g this b it an d b it 0 simultaneously hi g h will hol d the p c lk2 pin low. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2dh 0 divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk2 b y two. note: s ettin g this b it an d b it 1 simultaneously hi g h will hol d the p c lk2 pin low. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 92 of 119 p c lk3_phase/divi d e 2eh 15- 6 reserve d . s et these b its to zero when writin g to 2eh. ?? 2eh 5-2 p c lk3_phase - a d justs the output phase of the p c lk3/p c lk3 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2eh 1 divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk3/p c lk3 b y four. s ettin g this b it an d b it 0 simultaneously hi g h will g ive the full rate vi d eo c lo c k on the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 2eh 0 divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk3/p c lk3 b y two. s ettin g this b it an d b it 1 simultaneously hi g h will g ive the full rate vi d eo c lo c k on the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 0 p c lk3_tristate 2fh 15-2 reserve d . s et these b its to zero when writin g to 2fh. ?? 2fh 1-0 s et these b its to 11 b to tristate the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 6 1 r/w 00 b r s vd 2fh - 30h ? reserve d .?? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 93 of 119 au d io_ c ontrol ( gs 4911b only) 31h 15-10 reserve d . s et these b its to zero when writin g to 31h. ?? 31h 9-7 af s _reset_win d ow - these b its may b e use d to a d just the value b y whi c h the au d io c lo c k c ounters are allowe d to d rift from the output af s pulse. the en c o d in g s c heme for this re g ister is shown in ta b le 3-9 . note: the d efault settin g of this re g ister will provi d e a reset win d ow that is suffi c ient for most stan d ar d s. to maintain c orre c t au d io c lo c k frequen c ies for some ve s a stan d ar d s, the reset win d ow may have to b e in c rease d from its d efault settin g . in this c ase, set the value of this re g ister to 1xx. s ee ta b le 3-9 . referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 010 b 31h 6 up d ate_ c ustom_a_ c lo c k - this b it is use d to up d ate the c ustom au d io c lo c k parameters pro g ramme d in re g isters 33h to 3 6 h of the host interfa c e. all non-zero parameters in these re g isters will b e up d ate d via a low to hi g h transition on this b it. r/w 0 31h 5 ena b le_384fs - set this b it hi g h to ena b le the 384fs an d 192fs au d io c lo c k outputs. this must b e set in a dd ition to re g isters 3fh to 41h. note: if this b it is hi g h, then a 512fs au d io c lo c k will have a 33% d uty c y c le when fs = 9 6 khz. referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 0 31h 4-3 reserve d . s et these b its to zero when writin g to 31h. ?? 31h 2 host_a s r_ s el - set this b it hi g h to sele c t the au d io sample rate usin g re g ister 32h instea d of the external a s r_ s el[2:0] pins. the external a s r_ s el[2:0] pins will b e i g nore d , b ut shoul d not b e left floatin g . referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 0 31h 1 af s _f_pulse - set this b it to 1 to stret c h the af s pulse d uration from 1 line to 1 fiel d . referen c e: s e c tion 3.8.2 on pa g e 6 8 r/w 0 31h 0 af s _reset_disa b le - set this b it hi g h to d isa b le the 10fid input referen c e pin from resettin g the output af s pulse. if this b it is set hi g h, the output af s pulse will free-run or may b e reset usin g re g ister 1ah. the external 10fid pin shoul d not b e left floatin g . referen c e: s e c tion 3.8.2 on pa g e 6 8 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 94 of 119 a s r_ s el[2:0] ( gs 4911b only) 32h 15-3 reserve d . s et these b its to zero when writin g to 32h. ?? 32h 2-0 repla c es the external a s r_ s el[2:0] pins when host_a s r_ s ele c t ( b it 2 of a dd ress 31h) is hi g h. the d efault settin g of this re g ister c orrespon d s to an au d io sample rate of 48khz. referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 011 b n a ( gs 4911b only) 34h-33h 31-0 a non-zero num b er pro g ramme d in this re g ister d efines the numerator fo r the ratio of the au d io c lo c k to the 27mhz referen c e. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 31h. the d efault value of this re g ister will vary d epen d in g on the output au d io rate sele c te d . a dd ress 33h = b its 15-0 a dd ress 34h = b its 31-1 6 referen c e: s e c tion 3.9.2 on pa g e 73 . r/w ? d a ( gs 4911b only) 3 6 h-35h 31-0 a non-zero num b er pro g ramme d in this re g ister d efines the d enominator for th e ratio of the au d io c lo c k to the 27mhz referen c e. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 31h. the d efault value of this re g ister will vary d epen d in g on the output au d io rate sele c te d . a dd ress 35h = b its 15-0 a dd ress 3 6 h = b its 31-1 6 referen c e: s e c tion 3.9.2 on pa g e 73 . r/w ? r s vd 37h - 38h ? reserve d .?? au d io_ c ap_ g enlo c k ( gs 4911b only) 39h 15- 6 reserve d . s et these b its to zero when writin g to 39h. ?? 39h 5-0 c ontrol si g nal to a d just loop b an d wi d th of au d io g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 10 an d au d io_res_ g enlo c k - 21. the d efault value of this re g ister will d epen d on the fun d amental samplin g frequen c y sele c te d . referen c e: s e c tion 3. 6 .4 on pa g e 58 r/w ? au d io_res_ g enlo c k ( gs 4911b only) 3ah 15- 6 reserve d . s et these b its to zero when writin g to 3ah. ?? 3ah 5-0 c ontrol si g nal to a d just loop b an d wi d th of au d io g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 32 an d 42. the d efault value of this re g ister will d epen d on the fun d amental samplin g frequen c y sele c te d . referen c e: s e c tion 3. 6 .4 on pa g e 58 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 95 of 119 a_fee db a c k_divi d e ( gs 4911b only) 3 c h-3bh 31-0 in the internal au d io g enlo c k b lo c k, this re g ister d efines the numerator of the d ivi d e ratio. this re g ister may b e pro g ramme d to manually g enlo c k the au d io c lo c k to the vi d eo c lo c k. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 3bh = b its 15-0 a dd ress 3 c h = b its 31-1 6 referen c e: s e c tion 3. 6 .2.2 on pa g e 5 6 r/w ? a_referen c e_divi d e ( gs 4911b only) 3eh-3dh 31-0 in the internal au d io g enlo c k b lo c k, this re g ister d efines the d enominator of the d ivi d e ratio. this re g ister may b e pro g ramme d to manually g enlo c k the au d io c lo c k to the vi d eo c lo c k. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . a dd ress 3dh = b its 15-0 a dd ress 3eh = b its 31-1 6 referen c e: s e c tion 3. 6 .2.2 on pa g e 5 6 r/w ? a c lk1_fs_multiple ( gs 4911b only) 3fh 15-3 reserve d . s et these b its to zero when writin g to 3fh. ?? 3fh 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk1 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 0 a c lk2_fs_multiple ( gs 4911b only) 40h 15-3 reserve d . s et these b its to zero when writin g to 40h. ?? 40h 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk2 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 96 of 119 a c lk3_fs_multiple ( gs 4911b only) 41h 15-3 reserve d . s et these b its to zero when writin g to 41h. ?? 41h 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk3 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 6 3 r/w 0 r s vd 42h ? reserve d .?? output_ s ele c t_1 43h 15-5 reserve d . s et these b its to zero when writin g to 43h. ?? 43h 4 c urrent_1 - sele c ts the c urrent d rive c apa b ility of the timin g _out_1 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 43h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_1 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0001 b , whi c h c orrespon d s to h s yn c . referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0001 b output_ s ele c t_2 44h 15-5 reserve d . s et these b its to zero when writin g to 44h. ?? 44h 4 c urrent_2 - sele c ts the c urrent d rive c apa b ility of the timin g _out_2 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 44h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_2 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0010 b , whi c h c orrespon d s to h blankin g . referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0010 b table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 97 of 119 output_ s ele c t_3 45h 15-5 reserve d . s et these b its to zero when writin g to 45h. ?? 45h 4 c urrent_3 - sele c ts the c urrent d rive c apa b ility of the timin g _out_3 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 45h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_3 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0011 b , whi c h c orrespon d s to v s yn c . referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0011 b output_ s ele c t_4 4 6 h 15-5 reserve d . s et these b its to zero when writin g to 4 6 h. ?? 4 6 h4 c urrent_4 - sele c ts the c urrent d rive c apa b ility of the timin g _out_4 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 4 6 h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_4 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0100 b , whi c h c orrespon d s to v blankin g . referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0100 b output_ s ele c t_5 47h 15-5 reserve d . s et these b its to zero when writin g to 47h. ?? 47h 4 c urrent_5 - sele c ts the c urrent d rive c apa b ility of the timin g _out_5 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 47h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_5 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0101 b , whi c h c orrespon d s to f s yn c . referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0101 b table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 98 of 119 output_ s ele c t_ 6 48h 15-5 reserve d . s et these b its to zero when writin g to 48h. ?? 48h 4 c urrent_ 6 - sele c ts the c urrent d rive c apa b ility of the timin g _out_ 6 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 48h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_ 6 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0110 b , whi c h c orrespon d s to f di g ital. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0110 b output_ s ele c t_7 49h 15-5 reserve d . s et these b its to zero when writin g to 49h. ?? 49h 4 c urrent_7 - sele c ts the c urrent d rive c apa b ility of the timin g _out_7 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 49h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_7 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0111 b , whi c h c orrespon d s to 10fid. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0111 b output_ s ele c t_8 4ah 15-5 reserve d . s et these b its to zero when writin g to 4ah. ?? 4ah 4 c urrent_8 - sele c ts the c urrent d rive c apa b ility of the timin g _out_8 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 71 r/w 0 4ah 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_8 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 1000 b , whi c h c orrespon d s to display ena b le (de). referen c e: s e c tion 3.8.4 on pa g e 71 r/w 1000 b r s vd 4bh ? reserve d .?? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 99 of 119 vi d eo_ c ontrol 4 c h 15-5 reserve d . s et these b its to zero when writin g to 4 c h. ?? 4 c h 4 10fid_f_pulse - set this b it hi g h to stret c h the 10fid pulse d uration from 1 line to 1 fiel d . referen c e: s e c tion 3.8.1 on pa g e 6 7 r/w 0 4 c h 3-2 reserve d . s et these b its to zero when writin g to 4 c h. ?? 4 c h 1 host_vid_ s td - set this b it hi g h to sele c t the output vi d eo stan d ar d usin g re g ister 4dh instea d of the external vid_ s td[5:0] pins. the external vid_ s td[5:0] pins will b e i g nore d , b ut shoul d not b e left floatin g . referen c e: s e c tion 1.4 on pa g e 20 r/w 0 4 c h 0 reserve d . s et this b it to zero when writin g to 4 c h. ? ? vid_ s td[5:0] 4dh 15- 6 reserve d . s et these b its to zero when writin g to 4dh. ?? 4dh 5-0 repla c es the external vid_ s td[5:0] pins when vid_from_host ( b it 1 of a dd ress 4 c h) is hi g h. referen c e: s e c tion 1.4 on pa g e 20 r/w 00h c lo c ks_per_line 4eh 15-0 c ontains the num b er of output vi d eo c lo c k c y c les per line for the sele c te d output timin g format. if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. referen c e: s e c tion 3.10 on pa g e 74 r/w ? c lo c ks_per_hsyn c 4fh 15-0 c ontains the num b er of output vi d eo c lo c k c y c les in the a c tive h s yn c interval for the sele c te d output timin g format. if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. referen c e: s e c tion 3.10 on pa g e 74 r/w ? hsyn c _to_ s av 50h 15-0 c ontains the num b er of output vi d eo c lo c k c y c les from the start of h s yn c to the start of a c tive vi d eo for the sele c te d output timin g format. if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. referen c e: s e c tion 3.10 on pa g e 74 r/w ? hsyn c _to_eav 51h 15-0 c ontains the num b er of output vi d eo c lo c k c y c les from the start of h s yn c to the en d of a c tive vi d eo for the sele c te d output timin g format. if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. referen c e: s e c tion 3.10 on pa g e 74 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 100 of 119 lines_per_fiel d 52h 15-0 c ontains the num b er of lines per fiel d for the sele c te d output timin g format. this re g ister is 15.1 en c o d e d (i.e. b it 0 represents 0.5 when set hi g h an d 0 when set low). if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. note: when b it 0 of this re g ister is pro g ramme d hi g h, the d evi c e assumes an interla c e d output. otherwise it assumes a pro g ressive output. for example, pro g rammin g ?2 6 2.5? d will result in an interla c e d output stan d ar d with 525 lines per frame. pro g rammin g ?525? d will result in a pro g ressive output with 525 lines per frame. referen c e: s e c tion 3.10 on pa g e 74 r/w ? lines_per_vsyn c 53h 15-0 c ontains the num b er of lines per a c tive v s yn c interval for the sele c te d output timin g format. this re g ister is 15.1 en c o d e d (i.e. b it 0 represents ' 0.5 ' when set hi g h an d ' 0 ' when set low). if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. referen c e: s e c tion 3.10 on pa g e 74 r/w ? vsyn c _to_first_a c tive_line 54h 15-0 c ontains the num b er of lines from the start of v s yn c to the start of a c tive vi d eo for the sele c te d output timin g format. this re g ister is 15.1 en c o d e d (i.e. b it 0 represents ' 0.5 ' when set hi g h an d ' 0 ' when set low). if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. note1: the value pro g ramme d in this re g ister will b e in c rease d b y 1 b y the d evi c e su c h that v blankin g si g nal g enerate d will b e one line lon g er than pro g ramme d . note2: for the pre-pro g ramme d output vi d eo stan d ar d s 3, 5, an d 7, the value c ontaine d in this re g ister is in c orre c tly reporte d as 17 lines, althou g h the a c tual timin g pro d u c e d is c orre c t at 1 6 lines. referen c e: s e c tion 3.10 on pa g e 74 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 101 of 119 vsyn c _to_last_a c tive_line 55h 15-0 c ontains the num b er of lines from the start of v s yn c to the en d of a c tive vi d eo for the sele c te d output timin g format. this re g ister is 15.1 en c o d e d (i.e. b it 0 represents ' 0.5 ' when set hi g h an d ' 0 ' when set low). if vid_ s td[5:0] = 6 2, this re g ister may b e set b y the user when pro g rammin g c ustom output timin g si g nals. otherwise, this re g ister is rea d -only. note: the user c annot spe c ify a c ustom verti c al b lankin g si g nal to en d in the mi dd le of a line. if this o cc urs, the d evi c e will automati c ally a d just the timin g of the si g nal to fall at the b e g innin g of the next line. referen c e: s e c tion 3.10 on pa g e 74 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 102 of 119 polarity 5 6 h 15-10 reserve d . s et these b its to zero when writin g to 5 6 h. ?? 5 6 h9af s ( gs 4911b only)- set this b it hi g h to invert the polarity of the af s timin g output si g nal. by d efault, the af s si g nal is hi g h for the d uration of the first line of the n?th vi d eo frame to in d i c ate that the a c lk d ivi d ers have b een reset at the start of line 1 of that frame. note: the gs 4910b d oes not g enerate an af s pulse an d will i g nore the settin g of this b it. referen c e: ta b le 1-3 r/w 0 5 6 h 8 10fid - set this b it hi g h to invert the polarity of the 10fid timin g output si g nal. by d efault, the 10fid si g nal will g o hi g h for one line at the start of the 10-fiel d sequen c e. referen c e: ta b le 1-3 r/w 0 5 6 h 7 de - set this b it hi g h to invert the polarity of the de timin g output si g nal. by d efault, the de si g nal will b e hi g h whenever pixel information is to b e d isplaye d on the d isplay d evi c e referen c e: ta b le 1-3 r/w 0 5 6 h 6 reserve d . s et this b it to zero when writin g to 5 6 h. ? ? 5 6 h 5 f_di g ital - set this b it hi g h to invert the polarity of the f di g ital timin g output si g nal. by d efault, the f di g ital si g nal will b e low for the entire perio d of fiel d 1. referen c e: ta b le 1-3 r/w 0 5 6 h4f_ s yn c - set this b it hi g h to invert the polarity of the f s yn c timin g output si g nal. by d efault, the f s yn c si g nal will b e hi g h for the entire perio d of fiel d 1. referen c e: ta b le 1-3 r/w 0 5 6 h3v_blankin g - set this b it hi g h to invert the polarity of the v blankin g timin g output si g nal. by d efault, the v blankin g si g nal will b e low for the portion of the fiel d /frame c ontainin g vali d vi d eo d ata. referen c e: ta b le 1-3 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 103 of 119 5 6 h2v_ s yn c - set this b it hi g h to invert the polarity of the v s yn c timin g output si g nal. by d efault, the v s yn c si g nal is a c tive low. referen c e: ta b le 1-3 r/w 0 5 6 h 1 h_blankin g - set this b it hi g h to invert the polarity of the h blankin g timin g output si g nal. by d efault, the h blankin g si g nal will b e low for the portion of the vi d eo line c ontainin g vali d vi d eo samples. referen c e: ta b le 1-3 r/w 0 5 6 h0h_ s yn c - set this b it hi g h to invert the polarity of the h s yn c timin g output si g nal. by d efault, the h s yn c si g nal is a c tive low. referen c e: ta b le 1-3 r/w 0 h_ s tart_1 57h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er1_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_1. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 h_ s top_1 58h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er1_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s tart_1 59h 15 reserve d . s et this b it to zero when writin g to 59h. ? ? 59h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er1_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_1. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s top_1 5ah 15 reserve d . s et this b it to zero when writin g to 5ah. ? ? 5ah 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er1_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 104 of 119 operator_polarity_1 5bh 15-4 reserve d . s et these b its to zero when writin g to 5bh. ?? 5bh 3 polarity_1 - use this b it to invert the polarity of the final u s er1 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 1 5bh 2 and_1 - lo g i c al operator: u s er1_h and u s er1_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er1_h an d u s er1_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 5bh 1 or_1 - lo g i c al operator: u s er1_h or u s er1_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er1_h or u s er1_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 5bh 0 xor_1 - lo g i c al operator: u s er1_h xor u s er1_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er1_h or u s er1_v is a c tive. s i g nal is ina c tive when u s er1_h an d u s er1_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 h_ s tart_2 5 c h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er2_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_2 referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 h_ s top_2 5dh 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er2_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 105 of 119 v_ s tart_2 5eh 15 reserve d . s et this b it to zero when writin g to 5eh. ? ? 5eh 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er2_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_2. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s top_2 5fh 15 reserve d . s et this b it to zero when writin g to 5fh. ? ? 5fh 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er2_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 operator_polarity_2 6 0h 15-4 reserve d . s et these b its to zero when writin g to 6 0h. ?? 6 0h 3 polarity_2 - use this b it to invert the polarity of the final u s er2 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 1 6 0h 2 and_2 - lo g i c al operator: u s er2_h and u s er2_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er2_h an d u s er2_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 0h 1 or_2 - lo g i c al operator: u s er2_h or u s er2_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er2_h or u s er2_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 0h 0 xor_2 - lo g i c al operator: u s er2_h xor u s er2_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er2_h or u s er2_v is a c tive. s i g nal is ina c tive when u s er2_h an d u s er2_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 106 of 119 h_ s tart_3 6 1h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er3_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_3. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 h_ s top_3 6 2h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er3_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s tart_3 6 3h 15 reserve d . s et this b it to zero when writin g to 6 3h. ? ? 6 3h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er3_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_3. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s top_3 6 4h 15 reserve d . s et this b it to zero when writin g to 6 4h. ? ? 6 4h 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er3_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 107 of 119 operator_polarity_3 6 5h 15-4 reserve d . s et these b its to zero when writin g to 6 5h. ?? 6 5h 3 polarity_3 - use this b it to invert the polarity of the final u s er3 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 1 6 5h 2 and_3 - lo g i c al operator: u s er3_h and u s er3_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er3_h an d u s er3_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 5h 1 or_3 - lo g i c al operator: u s er3_h or u s er3_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er3_h or u s er3_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 5h 0 xor_3 - lo g i c al operator: u s er3_h xor u s er3_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er3_h or u s er3_v is a c tive. s i g nal is ina c tive when u s er3_h an d u s er3_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 h_ s tart_4 66 h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er4_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_4. referen c e: s e c tion 3.8.3 r/w 0 h_ s top_4 6 7h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er4_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 108 of 119 v_ s tart_4 6 8h 15 reserve d . s et this b it to zero when writin g to 6 8h. ? ? 6 8h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er4_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_4. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 v_ s top_4 6 9h 15 reserve d . s et this b it to zero when writin g to 6 9h. ? ? 6 9h 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er4_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 operator_polarity_4 6 ah 15-4 reserve d . s et these b its to zero when writin g to 6 ah. ?? 6 ah 3 polarity_4 - use this b it to invert the polarity of the final u s er4 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 1 6 ah 2 and_4 - lo g i c al operator: u s er4_h and u s er4_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er4_h an d u s er4_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 ah 1 or_4 - lo g i c al operator: u s er4_h or u s er4_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er4_h or u s er4_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 6 ah 0 xor_4 - lo g i c al operator: u s er4_h xor u s er4_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er4_h or u s er4_v is a c tive. s i g nal is ina c tive when u s er4_h an d u s er4_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 9 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 109 of 119 ext_au d io_mo d e 81h 15-0 s et this re g ister to 20 c 1h to ena b le the exten d e d au d io mo d e of the d evi c e. to fully ena b le this mo d e, vid_ s td[5:0] must b e set to 4 d , an d the f_lo c k_mask an d v_lo c k_mask b its [4:3] of re g ister a dd ress 1 6 h must b e set to 1. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 1 6 h. referen c e: s e c tion 3.11 on pa g e 75 r/w 0 ln_ c ount_reset 83h 15 to gg le this b it to reset the line- b ase d c ounters in the d evi c e. this is only require d when lo c kin g the ?f/1.001? hd output stan d ar d s to the 525-line s d input referen c e stan d ar d s, or vi c e-versa, and: 1. the reference has been removed and subsequently re-applied. in this case, the user should wait until the reference has been re-detected by the device, which may take up to 4 frames. see section 3.5.3 on page 47 . or 2. the device is locked to blanking signals from a deserializer, and the sdi input to the deserializer has been switched upstream from the system. see section 3.6.5 on page 60 . r/w 0 83h 14-0 reserve d . s et these b its to zero when writin g to 83h. ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 110 of 119 3.13 jtag when the jtag/host input pin of the gs4911b/gs4910b is set high, the host interface port will be configured for jtag test operation. in this mode, pins 57 through 60 become tclk, tdi, tdo, and tms. in addition, the reset pin will operate as the test reset pin. boundary scan testing usin g the jtag interface will be enabled in this mode. there are two methods in which jtag can be used on the gs4911b/gs4910b: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applicatio ns such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with high-impedance buffers used in conjunction with the jtag/host input signal. this is shown in figure 3-19 . fi g ure 3-19: in- c ir c uit j ta g alternatively, if the test capabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 3-20 . application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 111 of 119 fi g ure 3-20: s ystem j ta g note: when running boun dary scan testing, the timing_o ut_n pins should be set to high-impedance by sett ing vid_stdn to 000h. 3.14 device power-up 3.14.1 power supply sequencing the gs4911b/gs4910b has a reco mmended power supply sequen ce. to ensu re correct power-up, the analog_vdd and core_vdd power pins should be powered before io_vdd. device pins may be driven prior to power-up without causing damage. 3.15 device reset in order to initialize operating conditions to their default states, the application layer must hold the reset signal low during power up and for a minimum of 500us after the last supply has reached its operating voltage. application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe tri-state gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 112 of 119 4. application reference design 4.1 gs4911b typical application circuit note: for a solution with th e lowest output jitter, the gs1531 or gs1532 serializers are recommended for use with the gs4911b/gs4910b. c ontrolle d impe d an c e 100-ohms d ifferential note: the gs 4911a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must b e g roun d e d if it will not b e use d vid_pll_ g nd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_ g nd 8 c ore_ g nd 9 ph s _ g nd 55 ph s _vdd 54 analo g _vdd 10 n c 11 analo g _ g nd 12 aud_pll_ g nd 13 aud_pll_vdd 14 10fid 15 h s yn c 1 6 v s yn c 17 io_vdd 18 f s yn c 19 n c 20 vid_ s td0 21 vid_ s td1 22 vid_ s td2 23 vid_ s td3 24 vid_ s td4 25 vid_ s td5 27 a c lk1 28 a c lk2 29 a c lk3 30 io_vdd 31 c ore_vdd 2 6 a s r_ s el2 32 a s r_ s el1 33 a s r_ s el0 34 timin g _out1 35 timin g _out2 3 6 io_vdd 38 timin g _out4 39 timin g _out3 37 timin g _out5 40 lvd s /p c lk3_vdd 45 p c lk3 4 6 lvd s /p c lk3_ g nd 48 p c lk3 47 p c lk2 49 p c lk1&2_ g nd 52 p c lk1 51 io_vdd 50 timin g _out 6 41 timin g _out7 42 timin g _out8 43 p c lk1&2_vdd 53 lo c k_lo s t 1 ref_lo s t 2 g enlo c k 6 4 c ore_vdd 44 j ta g /ho s t 5 6 sc lk_t c lk 57 s din_tdi 58 s dout_tdo 59 cs _tm s 6 0 re s et 6 1 io_vdd 6 2 n c 6 3 g nd_pad 6 5 22r 10n 10n 10n 10n 22r 22r 22r 22r 10n 0r 22r 10n 22r 24pf 10n 22r 22r gs 4911b 10n 38pf 10n 22r 22r 10n 10n 1m 22r 10n 10n 22r 1v8_p c lk vdd_io 1v8_ c ore g nd_xtal 1v8_ c ore vdd_io vdd_io 1v8_vpll 1v8_vpll g nd_vpll 1v8_p c lk vdd_io g nd_vpll 1v8_apll g nd_apll vdd_xtal g nd_xtal h s yn c v s yn c f s yn c 10fid a c lk3 a c lk2 a c lk1 timin g 1 timin g 2 timin g 3 timin g 4 timin g 5 timin g6 timin g 7 timin g 8 csb re s et b s din s dout sc lk p c lk2 p c lk3 p c lk3 b p c lk1 g enlo c k b j ta g /ho s t b vid_ s td0 vid_ s td1 vid_ s td2 vid_ s td3 vid_ s td4 vid_ s td5 a s r_ s el0 a s r_ s el2 a s r_ s el1 lo c k_lo s t ref_lo s t 27mhz gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 113 of 119 4.2 gs4910b typical application circuit note: for a solution with th e lowest output jitter, the gs1531 or gs1532 serializers are recommended for use with the gs4911b/gs4910b. c ontrolle d impe d an c e 100-ohms d ifferential note: the gs 4910a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must b e g roun d e d if it will not b e use d vid_pll_ g nd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_ g nd 8 c ore_ g nd 9 ph s _ g nd 55 ph s _vdd 54 analo g _vdd 10 n c 11 analo g _ g nd 12 analo g _ g nd 13 analo g _ g nd 14 10fid 15 h s yn c 1 6 v s yn c 17 io_vdd 18 f s yn c 19 n c 20 vid_ s td0 21 vid_ s td1 22 vid_ s td2 23 vid_ s td3 24 vid_ s td4 25 vid_ s td5 27 n c 28 n c 29 n c 30 io_vdd 31 c ore_vdd 2 6 analo g _ g nd 32 analo g _ g nd 33 analo g _ g nd 34 timin g _out1 35 timin g _out2 3 6 io_vdd 38 timin g _out4 39 timin g _out3 37 timin g _out5 40 lvd s /p c lk3_vdd 45 p c lk3 4 6 lvd s /p c lk3_ g nd 48 p c lk3 47 p c lk2 49 p c lk1&2_ g nd 52 p c lk1 51 io_vdd 50 timin g _out 6 41 timin g _out7 42 timin g _out8 43 p c lk1&2_vdd 53 lo c k_lo s t 1 ref_lo s t 2 g enlo c k 6 4 c ore_vdd 44 j ta g /ho s t 5 6 sc lk_t c lk 57 s din_tdi 58 s dout_tdo 59 cs _tm s 6 0 re s et 6 1 io_vdd 6 2 n c 6 3 g nd_pad 6 5 10n 10n 10n 10n 22r 22r 22r 10n 0r 10n 24pf 22r 10n 22r 22r gs 4910b 10n 38pf 10n 22r 10n 22r 1m 10n 22r 10n 10n 22r 1v8_p c lk vdd_io 1v8_ c ore g nd_xtal 1v8_ c ore vdd_io vdd_io 1v8_vpll 1v8_vpll g nd_vpll 1v8_p c lk vdd_io g nd_vpll g nd_a vdd_xtal g nd_xtal 1v8_a g nd_a g nd_a h s yn c v s yn c f s yn c 10fid timin g 1 timin g 2 timin g 3 timin g 4 timin g 5 timin g6 timin g 7 timin g 8 csb re s et b s din s dout sc lk p c lk2 p c lk3 p c lk3 b p c lk1 g enlo c k b j ta g /ho s t b vid_ s td0 vid_ s td1 vid_ s td2 vid_ s td3 vid_ s td4 vid_ s td5 lo c k_lo s t ref_lo s t 27mhz gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 114 of 119 5. references & relevant standards table 5-1: references & relevant standards ae s 11-1997 s yn c hronization of di g ital au d io equipment in s tu d io operations s mpte 125m-1995 c omponent vi d eo s i g nal 4:2:2 ? bit-parallel di g ital interfa c e s mpte 170m-1999 c omposite analo g vi d eo s i g nal ? nt sc for s tu d io appli c ations s mpte 244m-1995 s ystem m/nt sc c omposite vi d eo s i g nals ? bit-parallel di g ital interfa c e s mpte 2 6 0m-1999 1125/ 6 0 hi g h-definition pro d u c tion s ystem ? di g ital representation an d bit-parallel interfa c e s mpte 2 6 7m-1995 bit-parallel di g ital interfa c e ? c omponent vi d eo s i g nal 4:2:2 1 6 x9 aspe c t ratio s mpte 274m-1998 1920 x 1080 sc annin g an d analo g an d parallel di g ital interfa c es for multiple pi c ture rates s mpte 293m-199 6 720 x 483 a c tive line at 59.94-hz pro g ressive sc an pro d u c tion ? di g ital representation s mpte 29 6 m-1997 1280 x 720 sc annin g , analo g an d di g ital representation an analo g interfa c e s mpte 318m-1999 s yn c hronization of 59.94- or 50-hz relate d vi d eo an d au d io s ystems in analo g an d di g ital areas ? referen c e s i g nals s mpte 347m-2001 540 m b /s s erial di g ital interfa c e ? s our c e ima g e format mappin g s mpte rp 1 6 4-199 6 lo c ation of verti c al interval time c o d e s mpte rp 1 6 8-1993 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g s mpte rp 211-2000 implementation of 24p, 25p an d 30p s e g mente d frames for 1920 x 1080 pro d u c tion format itu-r bt. 6 01-5 s tu d io en c o d in g parameters of di g ital television for s tan d ar d 4:3 an d wi d e-s c reen 1 6 :9 aspe c t ratios itu-r bt.709-4 parameter values for the hdtv s tan d ar d s for pro d u c tion an d international pro g ram ex c han g e itu-r bt.799.3 interfa c e for di g ital c omponent vi d eo s i g nals in 525-line an d 6 25-line television s ystems operatin g at the 4:4:4 level of re c ommen d ation itu-r bt. 6 01 (part a) itu-r bt.1358 s tu d io parameters of 6 25 an d 525 line pro g ressive sc an television s ystems ve s a monitor timin g s pe c ifi c ations ve s a an d in d ustry s tan d ar d s an d g ui d elines for c omputer display monitor timin g ? version 1.0, revision 0.8 (a d option date: s eptem b er 17, 1998) gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 115 of 119 6. package & ordering information 6.1 package dimensions a b 9.00 4.50 4.50 9.00 2x 2x 0.15 c 0.15 c 0.10 c 0.08 c 64x seating plane 0.90 +/- 0.10 +0.03 0.02-0.02 0.20 ref c 7.10+/-0.15 3.55 0.40+/-0.05 7.10+/-0.15 3.55 0.25+/-0.05 64x 0.10 c ab c 0.05 0.50 all dimensions in mm pin 1 area centre tab 45 45 gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 116 of 119 6.2 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 6-1 . the recommended standard pb reflow profile is shown in figure 6-2 . fi g ure 6 -1: maximum p b -free s ol d er reflow profile (preferre d ) fi g ure 6 -2: s tan d ar d p b s ol d er reflow profile 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max 25c 100c 150c 183c 230c 220c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3c/sec max 6c/sec max gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 117 of 119 6.3 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensions shou ld conform to customer design rules and process optimizations. 6.4 packaging data note: all d imensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 c enter pad parameter value pa c ka g e type 9mm x 9mm 6 4-pin qfn moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 9.3 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 24. 6 c /w psi, 0.2 c /w p b -free an d roh s c ompliant yes gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 118 of 119 6.5 ordering information part video clocks graphics clocks audio clocks full programmability max pclk rate gs 4911b ?? 1 6 5mhz gs 4910b ? ? 1 6 5mhz part number package temperature range gs 4911b c ne3 p b -free 6 4-pin qfn 0 c to 70 c gs 4910b c ne3 p b -free 6 4-pin qfn 0 c to 70 c ottawa 232 herz b er g roa d , s uite 101 kanata, ontario k2k 2a1 c ana d a phone: +1 ( 6 13) 270-0458 fax: +1 ( 6 13) 270-0429 calgary 3553 - 31st s t. n.w., s uite 210 c al g ary, al b erta t2l 2k7 c ana d a phone: +1 (403) 284-2 6 72 united kingdom north buil d in g , wal d en c ourt parsona g e lane, bishop?s s tortfor d hertfor d shire, c m23 5db unite d kin gd om phone: +44 1279 714170 fax: +44 1279 714171 india #208(a), nirmala plaza, airport roa d , forest park s quare bhu b aneswar 751009 in d ia phone: +91 ( 6 74) 6 53-4815 fax: +91 ( 6 74) 259-5733 snowbush ip - a division of gennum 439 university ave. s uite 1700 toronto, ontario m5 g 1y8 c ana d a phone: +1 (41 6 ) 925-5 6 43 fax: +1 (41 6 ) 925-0581 e-mail: sales@snow b ush. c om we b s ite: http://www.snow b ush. c om mexico 288-a paseo d e maravillas j esus ma., a g uas c alientes mexi c o 20900 phone: +1 (41 6 ) 848-0328 japan kk s hinjuku g reen tower buil d in g 27f 6 -14-1, nishi s hinjuku s hinjuku-ku, tokyo, 1 6 0-0023 j apan phone: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 e-mail: g ennum-japan@ g ennum. c om we b s ite: http://www. g ennum. c o.jp ta i w a n 6 f-4, no.51, s e c .2, keelun g r d . s inyi distri c t, taipei c ity 11502 taiwan r.o. c . phone: (88 6 ) 2-8732-8879 fax: (88 6 ) 2-8732-8870 e-mail: g ennum-taiwan@ g ennum. c om germany hain b u c henstra?e 2 80935 muen c hen (muni c h), g ermany phone: +49-89-35831 6 9 6 fax: +49-89-35804 6 53 e-mail: g ennum- g ermany@ g ennum. c om north america western region bayshore plaza 2107 n 1st s treet, s uite #300 s an j ose, c a 95131 unite d s tates phone: +1 (408) 392-9454 fax: +1 (408) 392-9427 e-mail: naw_sales@ g ennum. c om north america eastern region 4281 harvester roa d burlin g ton, ontario l7l 5m4 c ana d a phone: +1 (905) 6 32-299 6 fax: +1 (905) 6 32-2055 e-mail: nae_sales@ g ennum. c om korea 8f j innex lakeview bl dg . 6 5-2, ban g i d on g , s on g pa g u s eoul, korea 138-828 phone: +82-2-414-2991 fax: +82-2-414-2998 e-mail: g ennum-korea@ g ennum. c om document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. gs4911b/gs4910b hd/sd/graphics clock and timing generator with genlock data sheet 36655 - 5 june 2009 119 of 119 119 g ennum c orporation assumes no lia b ility for any errors or omissions in this d o c ument, or for the use of the c ir c uits or d evi c es d es c ri b e d herein. the sale of the c ir c uit or d evi c e d es c ri b e d herein d oes not imply any patent li c ense, an d g ennum makes no representation that the c ir c uit or d evi c e is free from patent infrin g ement. all other tra d emarks mentione d are the properties of their respe c tive owners. g ennum an d the g ennum lo g o are re g istere d tra d emarks of g ennum c orporation. ? c opyri g ht 2005 g ennum c orporation. all ri g hts reserve d . www. g ennum. c om gennum corporate headquarters 4281 harvester roa d , burlin g ton, ontario l7l 5m4 c ana d a phone: +1 (905) 6 32-299 6 fax: +1 (905) 6 32-2055 e-mail: c orporate@ g ennum. c om www. g ennum. c om caution ele c tro s tati c s en s itive devi c e s do not open pa c ka g e s or handle ex c ept at a s tati c -free work s tation |
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